Issued Patents All Time
Showing 51–75 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11347502 | Apparatus and method of improved insert instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2022-05-31 |
| 11275583 | Apparatus and method of improved insert instructions | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2022-03-15 |
| 11269630 | Interleaved pipeline of floating-point adders | Simon Rubanovich, Zeev Sperber | 2022-03-08 |
| 11263009 | Systems and methods for performing 16-bit floating-point vector dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2022-03-01 |
| 11188335 | Apparatuses, methods, and systems for hashing instructions | Regev Shemy, Zeev Sperber, Wajdi K. Feghali, Vinodh Gopal, Simon Rubanovich +5 more | 2021-11-30 |
| 11175891 | Systems and methods to perform floating-point addition with selected rounding | Simon Rubanovich, Zeev Sperber, Mrinmay Dutta | 2021-11-16 |
| 11176278 | Efficient rotate adder for implementing cryptographic basic operations | Simon Rubanovich, Regev Shemy, Onkar P Desai, Jose Yallouz | 2021-11-16 |
| 11169802 | Systems, apparatuses, and methods for fused multiply add | Robert Valentine, Galina Ryvchin, Piotr Majcher, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall +4 more | 2021-11-09 |
| 11093247 | Systems and methods to load a tile register pair | Raanan Sade, Simon Rubanovich, Zeev Sperber, Alexander Heinecke, Robert Valentine +5 more | 2021-08-17 |
| 11068263 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11068262 | Systems and methods for performing instructions to convert to 16-bit floating-point format | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-07-20 |
| 11036504 | Systems and methods for performing 16-bit floating-point vector dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-06-15 |
| 11036509 | Enabling removal and reconstruction of flag operations in a processor | Zeev Sperber, Tomer Weiner, Simon Rubanovich, Alex Gerber, Itai Ravid | 2021-06-15 |
| 11023235 | Systems and methods to zero a tile register pair | Raanan Sade, Simon Rubanovich, Zeev Sperber, Alexander Heinecke, Robert Valentine +6 more | 2021-06-01 |
| 11016731 | Using Fuzzy-Jbit location of floating-point multiply-accumulate results | Simon Rubanovich, Zeev Sperber | 2021-05-25 |
| 10990397 | Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator | Simon Rubanovich, Sagi Meller, Zeev Sperber, Jose Yallouz, Robert Valentine | 2021-04-27 |
| 10963246 | Systems and methods for performing 16-bit floating-point matrix dot product instructions | Alexander Heinecke, Robert Valentine, Mark J. Charney, Raanan Sade, Menachem Adelman +2 more | 2021-03-30 |
| 10942738 | Accelerator systems and methods for matrix operations | Zeev Sperber, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas +4 more | 2021-03-09 |
| 10866786 | Systems and methods for performing instructions to transpose rectangular tiles | Raanan Sade, Robert Valentine, Mark J. Charney, Simon Rubanovich, Zeev Sperber +5 more | 2020-12-15 |
| 10866807 | Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride | Elmoustapha Ould-Ahmed-Vall, Seth Abraham, Robert Valentine, Zeev Sperber | 2020-12-15 |
| 10824428 | Apparatuses, methods, and systems for hashing instructions | Regev Shemy, Zeev Sperber, Wajdi K. Feghali, Vinodh Gopal, Simon Rubanovich +5 more | 2020-11-03 |
| 10732970 | Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset | Seth Abraham, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Zeev Sperber | 2020-08-04 |
| 10719316 | Apparatus and method of improved packed integer permute instruction | Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney +1 more | 2020-07-21 |
| 10649733 | Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions | Cristina S. Anderson, Zeev Sperber, Simon Rubanovich, Benny Eitan | 2020-05-12 |
| 10623015 | Apparatus and method for vector compression | Simon Rubanovich, David M. Russinoff, John W. O'Leary, Zeev Sperber | 2020-04-14 |