XC

Xiangdong Chen

IBM: 53 patents #1,572 of 70,183Top 3%
Broadcom: 48 patents #129 of 9,346Top 2%
QU Qualcomm: 32 patents #718 of 12,104Top 6%
TSMC: 20 patents #1,647 of 12,232Top 15%
FS Freeescale Semiconductor: 5 patents #628 of 3,767Top 20%
Samsung: 4 patents #25,854 of 75,807Top 35%
CM Chartered Semiconductor Manufacturing: 3 patents #194 of 840Top 25%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
TL Tsmc Nanjing Company, Limited: 2 patents #45 of 113Top 40%
Infineon Technologies Ag: 1 patents #168 of 446Top 40%
HC Hangzhou Silan Microelectronics Co.: 1 patents #12 of 35Top 35%
NC Nari Technology Co.: 1 patents #18 of 79Top 25%
SC State Grid Jiangsu Electric Power Co.: 1 patents #90 of 343Top 30%
University Of Texas System: 1 patents #2,951 of 6,559Top 45%
Ford: 1 patents #9,341 of 17,473Top 55%
BC Beijing Baidu Netcom Science Technology Co.: 1 patents #804 of 1,823Top 45%
📍 Hsinchu, CA: #8 of 400 inventorsTop 2%
Overall (All Time): #5,053 of 4,157,543Top 1%
165
Patents All Time

Issued Patents All Time

Showing 26–50 of 165 patents

Patent #TitleCo-InventorsDate
11038344 Shunt power rail with short line effect John Jianhong Zhu, Haining Yang, Kern Rim 2021-06-15
10965289 Metal oxide semiconductor device of an integrated circuit Satyanarayana Sahu, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta 2021-03-30
10785043 Load shedding system, communication method and access apparatus thereof Jijun Yin, Qing CHEN, Zheng Wu, Xiao Lu, Hengzhi Cui +9 more 2020-09-22
10784345 Standard cell architecture for gate tie-off Venugopal Boynapalli, Hyeokjin Lim 2020-09-22
10777640 Standard cell architecture for gate tie-off Venugopal Boynapalli, Hyeokjin Lim 2020-09-15
10692808 High performance cell design in a technology with high density metal routing Renukprasad HIREMATH, Hyeokjin Lim, Foua Vang, Venugopal Boynapalli 2020-06-23
10600866 Standard cell architecture for gate tie-off Venugopal Boynapalli, Hyeokjin Lim 2020-03-24
10593700 Standard cell architecture with M1 layer unidirectional routing Mukul Gupta, Ohsang Kwon, Foua Vang, Stanley Seungchul Song, Kern Rim 2020-03-17
10490543 Placement methodology to remove filler Sorin Adrian Dobre, Hyeokjin Lim, Venugopal Boynapalli 2019-11-26
10483200 Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance Haining Yang, John Jianhong Zhu 2019-11-19
10431686 Integrated circuit (IC) employing a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity Haining Yang 2019-10-01
10236886 Multiple via structure for high performance standard cells Satyanarayana Sahu, Venugopal Boynapalli, Hyeokjin Lim, Mickael Malabry, Mukul Gupta 2019-03-19
10199462 Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance Haining Yang 2019-02-05
10175571 Hybrid coloring methodology for multi-pattern technology Hyeokjin Lim, Ohsang Kwon, Mickael Malabry, Jingwei Zhang, Raymond George Stephany +5 more 2019-01-08
9984029 Variable interconnect pitch for improved performance Kern Rim, Stanley Seungchul Song, Raymond George Stephany, John Jianhong Zhu, Ohsang Kwon +2 more 2018-05-29
9979381 Semi-data gated flop with low clock power/low internal power with minimal area overhead Seid Hadi Rasouli, Venugopal Boynapalli 2018-05-22
9960231 Standard cell architecture for parasitic resistance reduction Hyeokjin Lim, Satyanarayana Sahu, Venugopal Boynapalli 2018-05-01
9941377 Semiconductor devices with wider field gates for reduced gate resistance Haining Yang 2018-04-10
9887209 Standard cell architecture with M1 layer unidirectional routing Mukul Gupta, Ohsang Kwon, Foua Vang, Stanley Seungchul Song, Kern Rim 2018-02-06
9831272 Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches Venugopal Boynapalli, Satyanarayana Sahu, Hyeokjin Lim, Mukul Gupta 2017-11-28
9773866 Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance Haining Yang 2017-09-26
9755618 Low-area low clock-power flip-flop Seid Hadi Rasouli, Venugopal Boynapalli 2017-09-05
9640522 V1 and higher layers programmable ECO standard cells Satyanarayana Sahu, Vinod Gupta, Triveni Rachapalli 2017-05-02
9640480 Cross-couple in multi-height sequential cells for uni-directional M1 Mukul Gupta, Ohsang Kwon 2017-05-02
9634026 Standard cell architecture for reduced leakage current and improved decoupling capacitance Satyanarayana Sahu, Ramaprasath Vilangudipitchai, Dorav Kumar 2017-04-25