Issued Patents All Time
Showing 76–100 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8797823 | Implementing SDRAM having no RAS to CAS delay in write operation | Brian J. Connolly, Kyu-hyoun Kim | 2014-08-05 |
| 8799566 | Memory system with a programmable refresh cycle | Charles A. Kilmer, Kyu-hyoun Kim, Vipin Patel | 2014-08-05 |
| 8705307 | Memory system with dynamic refreshing | Joab D. Henderson, Hillery C. Hunter, Jeffrey A. Stuecheli | 2014-04-22 |
| 8697567 | Implementing decoupling devices inside a TSV DRAM stack | Joab D. Henderson, Kyu-hyoun Kim, Kenneth L. Wright | 2014-04-15 |
| 8659959 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2014-02-25 |
| 8639874 | Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device | Kevin C. Gower, Kyu-hyoun Kim, Dustin J. VanStee | 2014-01-28 |
| 8589769 | System, method and storage medium for providing fault detection and correction in a memory subsystem | Timothy J. Dell, Kevin C. Gower | 2013-11-19 |
| 8495328 | Providing frame start indication in a memory system having indeterminate read data latency | Paul W. Coteus, Kevin C. Gower, Robert B. Tremaine | 2013-07-23 |
| 8452919 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2013-05-28 |
| 8379459 | Memory system with delay locked loop (DLL) bypass control | Kevin C. Gower, Kyu-hyoun Kim | 2013-02-19 |
| 8327105 | Providing frame start indication in a memory system having indeterminate read data latency | Paul W. Coteus, Kevin C. Gower, Robert B. Tremaine | 2012-12-04 |
| 8307270 | Advanced memory device having improved performance, reduced power and increased reliability | Kyu-hyoun Kim, George Liang-Tai Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower +2 more | 2012-11-06 |
| 8296541 | Memory subsystem with positional read data latency | Kevin C. Gower, Kevin W. Kark, Mark W. Kellogg | 2012-10-23 |
| 8255635 | Claiming coherency ownership of a partial cache line of data | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jerry Don Lewis | 2012-08-28 |
| 8245105 | Cascade interconnect memory system with enhanced reliability | Timothy J. Dell, Kevin C. Gower, Michael R. Trombley | 2012-08-14 |
| 8185800 | System for error control coding for memories of different types and associated methods | Paul W. Coteus, Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd | 2012-05-22 |
| 8176391 | System to improve miscorrection rates in error control code through buffering and associated methods | Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Eric E. Retter, Barry M. Trager +3 more | 2012-05-08 |
| 8151042 | Method and system for providing identification tags in a memory system having indeterminate data response times | Paul W. Coteus, Kevin C. Gower, Robert B. Tremaine | 2012-04-03 |
| 8145868 | Method and system for providing frame start indication in a memory system having indeterminate read data latency | Paul W. Coteus, Kevin C. Gower, Robert B. Tremaine | 2012-03-27 |
| 8140942 | System, method and storage medium for providing fault detection and correction in a memory subsystem | Timothy J. Dell, Kevin C. Gower | 2012-03-20 |
| 8140936 | System for a combined error correction code and cyclic redundancy check code for a memory channel | Kevin C. Gower | 2012-03-20 |
| 8117401 | Interconnect operation indicating acceptability of partial data delivery | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jerry Don Lewis | 2012-02-14 |
| 8108619 | Cache management for partial cache line operations | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Jerry Don Lewis | 2012-01-31 |
| 8099570 | Methods, systems, and computer program products for dynamic selective memory mirroring | James A. O'Connor, Kanwal Bahri, Daniel James Henderson, Luis A. Lastras-Montano, Michael Mueller +6 more | 2012-01-17 |
| 8086936 | Performing error correction at a memory device level that is transparent to a memory channel | Kevin C. Gower | 2011-12-27 |