Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| D721712 | Device support for a power and data center | Norman R. Byrne, Timothy J. Warwick | 2015-01-27 |
| 8037253 | Method and apparatus for global ordering to insure latency independent coherence | Sanjay Vishin | 2011-10-11 |
| 7752627 | Leaky-bucket thread scheduler in a multithreading microprocessor | Darren M. Jones, Ryan C. Kinter, Sanjay Vishin | 2010-07-06 |
| 7644237 | Method and apparatus for global ordering to insure latency independent coherence | Sanjay Vishin | 2010-01-05 |
| 7613904 | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler | Darren M. Jones, Ryan C. Kinter, Kevin D. Kissell | 2009-11-03 |
| 7480769 | Microprocessor with improved data stream prefetching | Keith E. Diefendorff | 2009-01-20 |
| 7366092 | Hash and route hardware with parallel routing scheme | Laurent Moll, Barton Sano | 2008-04-29 |
| 7194582 | Microprocessor with improved data stream prefetching | Keith E. Diefendorff | 2007-03-20 |
| 6898675 | Data received before coherency window for a snoopy bus | Alexander Edward Okpisz | 2005-05-24 |
| 6615323 | Optimizing pipelined snoop processing | Jose M. Nunez, Marie Jeannette Sullivan | 2003-09-02 |
| 6484230 | Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction | Brian R. Konigsburg, Alexander Edward Okpisz, Bruce Joseph Ronchetti | 2002-11-19 |
| 6460133 | Queue resource tracking in a multiprocessor system | Jose M. Nunez | 2002-10-01 |
| 6430658 | Local cache-to-cache transfers in a multiprocessor system | Jose M. Nunez | 2002-08-06 |
| 6415362 | Method and system for write-through stores of varying sizes | James Nolan Hardage, Alexander Edward Okpisz | 2002-07-02 |
| 6408361 | Autonomous way specific tag update | James Nolan Hardage, Scott I. Remington | 2002-06-18 |
| 6338121 | Data source arbitration in a multiprocessor system | Jose M. Nunez | 2002-01-08 |
| 6324622 | 6XX bus with exclusive intervention | Alexander Edward Okpisz | 2001-11-27 |
| 6317806 | Static queue and index queue for storing values identifying static queue locations | Srinath Audityan, Robert Podnar | 2001-11-13 |
| 6272601 | Critical word forwarding in a multiprocessor system | Jose M. Nunez | 2001-08-07 |
| 6269360 | Optimization of ordered stores on a pipelined bus via self-initiated retry | James Nolan Hardage | 2001-07-31 |
| 6256713 | Bus optimization with read/write coherence including ordering responsive to collisions | Srinath Audityan, James Nolan Hardage | 2001-07-03 |
| 6249845 | Method for supporting cache control instructions within a coherency granule | Jose M. Nunez | 2001-06-19 |
| 6209073 | System and method for interlocking barrier operations in load and store queues | Alexander Edward Okpisz, Amy May Tuvell, Ronny Lee Arnold | 2001-03-27 |
| 6122692 | Method and system for eliminating adjacent address collisions on a pipelined response bus | Alexander Edward Okpisz | 2000-09-19 |
| 6119204 | Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization | Joseph Y. Chang, James Nolan Hardage, Jose M. Nunez | 2000-09-12 |