Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6021485 | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching | Kurt A. Feiste, John Stephen Muhich, Larry Edward Thatcher | 2000-02-01 |
| 6021467 | Apparatus and method for processing multiple cache misses to a single cache line | Brian R. Konigsburg, John Stephen Muhich, Larry Edward Thatcher | 2000-02-01 |
| 5931957 | Support for out-of-order execution of loads and stores in a processor | Brian R. Konigsburg, John Stephen Muhich, Larry Edward Thatcher | 1999-08-03 |
| 5913048 | Dispatching instructions in a processor supporting out-of-order execution | Hoichi Cheong, Hung Q. Le, John Stephen Muhich | 1999-06-15 |
| 5887161 | Issuing instructions in a processor supporting out-of-order execution | Hoichi Cheong, Hung Q. Le, John Stephen Muhich | 1999-03-23 |
| 5870612 | Method and apparatus for condensed history buffer | Hoichi Cheong, Hung Q. Le, John Stephen Muhich | 1999-02-09 |
| 5870582 | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched | Hoichi Cheong, Hung Q. Le, John Stephen Muhich | 1999-02-09 |
| 5864341 | Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding | Troy N. Hicks, Hung Q. Le, John Stephen Muhich | 1999-01-26 |
| 5860014 | Method and apparatus for improved recovery of processor state using history buffer | Hoichi Cheong, Hung Q. Le, John Stephen Muhich | 1999-01-12 |
| 5805849 | Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions | Paul J. Jordan, Brian R. Konigsburg, Hung Q. Le | 1998-09-08 |
| 5802571 | Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory | Brian R. Konigsburg, John Stephen Muhich | 1998-09-01 |
| 5796998 | Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system | David S. Levitan, John Stephen Muhich, Adam R. Talcott | 1998-08-18 |
| 5784604 | Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging | John Stephen Muhich, Terrence Matthew Potter | 1998-07-21 |
| 5721858 | Virtual memory mapping method and system for memory management of pools of logical partitions for bat and TLB entries in a data processing system | G. Jeannette McWilliams, Jack Wayne Kemp | 1998-02-24 |
| 5708790 | Virtual memory mapping method and system for address translation mapping of logical memory partitions for BAT and TLB entries in a data processing system | G. Jeanette McWilliams, Jack Wayne Kemp | 1998-01-13 |
| 5375214 | Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes | Jamshed H. Mirza | 1994-12-20 |
| 5357618 | Cache prefetch and bypass using stride registers | Jamshed H. Mirza | 1994-10-18 |
| 5348711 | Dental handpiece sterilizer | Kenneth A. Johnson | 1994-09-20 |
| 5276838 | Dynamically repositioned memory bank queues | Chitta L. Rao | 1994-01-04 |
| 5247645 | Dynamic memory mapper which supports interleaving across 2.sup.N +1, 2.sup. N .sup.N -1 number of banks for reducing contention during nonunit stride accesses | Jamshed H. Mirza | 1993-09-21 |
| 5058003 | Virtual storage dynamic address translation mechanism for multiple-sized pages | — | 1991-10-15 |