Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8515724 | Technology computer-aided design (TCAD)-based virtual fabrication | Rajiv V. Joshi, Keunwoo Kim | 2013-08-20 |
| 8472271 | Systems and methods for memory device precharging | James Dawson, Rajiv V. Joshi, Noam Jungmann, Elazar Kachir, Ehud Nir +1 more | 2013-06-25 |
| 8365118 | Broken-spheres methodology for improved failure probability analysis in multi-fail regions | Rajiv V. Joshi, Zhuo Li, Sani R. Nassif | 2013-01-29 |
| 8346528 | Equivalent device statistical modeling for bitline leakage modeling | Rajiv V. Joshi, Sani R. Nassif | 2013-01-01 |
| 8214190 | Methodology for correlated memory fail estimations | Rajiv V. Joshi, Sani R. Nassif | 2012-07-03 |
| 8214777 | On-chip leakage current modeling and measurement circuit | Rajiv V. Joshi, Jente B. Kuang, Sani R. Nassif | 2012-07-03 |
| 8208339 | Computer program product for controlling a storage device having per-element selectable power supply voltages | Rajiv V. Joshi, Jente B. Kuang, Sani R. Nassif, Hung C. Ngo | 2012-06-26 |
| 8184475 | Robust local bit select circuitry to overcome timing mismatch | Rajiv V. Joshi, Antonio R. Pelella, Sudesh Saroop | 2012-05-22 |
| 8170857 | In-situ design method and system for improved memory yield | Rajiv V. Joshi | 2012-05-01 |
| 7995418 | Method and computer program for controlling a storage device having per-element selectable power supply voltages | Rajiv V. Joshi, Jente B. Kuang, Sani R. Nassif, Hung C. Ngo | 2011-08-09 |
| 7885798 | Closed-loop modeling of gate leakage for fast simulators | Rajiv V. Joshi, Ying Liu, Sani R. Nassif, Jayakumaran Sivagnaname | 2011-02-08 |
| 7827018 | Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects | Chad A. Adams, Rajiv V. Joshi, Sani R. Nassif | 2010-11-02 |
| 7751267 | Half-select compliant memory cell precharge circuit | Rajiv V. Joshi, Jayakumaran Sivagnaname | 2010-07-06 |
| 7752580 | Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique | Sarah C. Braasch, Jason D. Hibbeler, Daniel N. Maynard, Sani R. Nassif, Evanthia Papadopoulou | 2010-07-06 |
| 7733720 | Method and system for determining element voltage selection control values for a storage device | Rajiv V. Joshi, Jente B. Kuang, Sani R. Nassif, Hung C. Ngo | 2010-06-08 |
| 7551508 | Energy efficient storage device using per-element selectable power supply voltages | Rajiv V. Joshi, Jente B. Kuang, Sani R. Nassif, Hung C. Ngo | 2009-06-23 |
| 7380225 | Method and computer program for efficient cell failure rate estimation in cell arrays | Rajiv V. Joshi, Sani R. Nassif | 2008-05-27 |