Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6088788 | Background completion of instruction and associated fetch request in a multithread processor | John Michael Borkenhagen, Sheldon B. Levenstein, Andrew Henry Wottreng, Duane A. Averill, James Ira Brookhouser | 2000-07-11 |
| 6076157 | Method and apparatus to force a thread switch in a multithreaded processor | John Michael Borkenhagen, William T. Flynn, Andrew Henry Wottreng | 2000-06-13 |
| 6061710 | Multithreaded processor incorporating a thread latch register for interrupt service new pending threads | Harold F. Kossman | 2000-05-09 |
| 6049867 | Method and system for multi-thread switching only when a cache miss occurs at a second or higher level | Ross E. Johnson, Harold F. Kossman, Steven R. Kunkel, Timothy John Mullins, James Allen Rose | 2000-04-11 |
| 6021481 | Effective-to-real address cache managing apparatus and method | Ronald Nick Kalla | 2000-02-01 |
| 5940877 | Cache address generation with and without carry-in | Thomas L. Jeremiah | 1999-08-17 |
| 5878243 | Apparatus for decreasing the cycle times of a data processing system | Nadeem Malik, Avijit Saha, Charles Gorham Ward | 1999-03-02 |
| 5802564 | Method and apparatus for increasing processor performance | Nadeem Malik, Avijit Saha, Charles Gorham Ward | 1998-09-01 |
| 5778208 | Flexible pipeline for interlock removal | Nadeem Malik, Avijit Saha | 1998-07-07 |
| 5652774 | Method and apparatus for decreasing the cycle times of a data processing system | Nadeem Malik, Avijit Saha, Charles Gorham Ward | 1997-07-29 |
| 5651136 | System and method for increasing cache efficiency through optimized data allocation | James L. Denton, Kevin Curtis Griffin, Ross E. Johnson, Steven R. Kunkel, Mikko H. Lipasti +1 more | 1997-07-22 |
| 5500942 | Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions | Stamatis Vassiliadis | 1996-03-19 |
| 5459844 | Predecode instruction compounding | Stamatis Vassiliadis, Bartholomew Blaner | 1995-10-17 |
| 5448746 | System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution | Stamatis Vassiliadis | 1995-09-05 |
| 5442767 | Address prediction to avoid address generation interlocks in computer systems | Stamatis Vassiliadis | 1995-08-15 |
| 5377336 | Improved method to prefetch load instruction data | Stamatis Vassiliadis | 1994-12-27 |
| 5355460 | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution | Stamatis Vassiliadis, Bartholomew Blaner | 1994-10-11 |
| 5197135 | Memory management for scalable compound instruction set machines with in-memory compounding | Stamatis Vassiliadis, Bartholomew Blaner | 1993-03-23 |