Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8031639 | Efficient probabilistic duplicate packet detector in computer networks | Carl A. Bender, Fu Chung Chang, Kevin J. Gildea, Rama K. Govindaraju, Jay R. Herring +1 more | 2011-10-04 |
| 8023417 | Failover mechanisms in RDMA operations | Robert S. Blackmore, Fu Chung Chang, Piyush Chaudhary, Jason E. Goscinski, Rama K. Govindaraju +4 more | 2011-09-20 |
| 7996593 | Interrupt handling using simultaneous multi-threading | Robert S. Blackmore, Rama K. Govindaraju | 2011-08-09 |
| 7890703 | Cache injection using semi-synchronous memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-15 |
| 7882321 | Validity of address ranges used in semi-synchronous memory copy operations | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2011-02-01 |
| 7813369 | Half RDMA and half FIFO operations | Robert S. Blackmore, Fu Chung Chang, Piyush Chaudhary, Kevin J. Gildea, Jason E. Goscinski +7 more | 2010-10-12 |
| 7774554 | System and method for intelligent software-controlled cache injection | Piyush Chaudhary, Rama K. Govindaraju, Jay R. Herring, Chulho Kim, Rajeev Sivaram +1 more | 2010-08-10 |
| 7634642 | Mechanism to save and restore cache and translation trace for fast context switch | Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski | 2009-12-15 |
| 7619993 | Efficient probabilistic duplicate packet detector in computer networks | Carl A. Bender, Fu Chung Chang, Kevin J. Gildea, Rama J. Govindaraju, Jay R. Herring +1 more | 2009-11-17 |
| 7523260 | Propagating data using mirrored lock caches | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-04-21 |
| 7506132 | Validity of address ranges used in semi-synchronous memory copy operations | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-03-17 |
| 7493436 | Interrupt handling using simultaneous multi-threading | Robert S. Blackmore, Rama K. Govindaraju | 2009-02-17 |
| 7484062 | Cache injection semi-synchronous memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2009-01-27 |
| 7477608 | Methods for routing packets on a linear array of processors | Monty M. Denneau, Richard A. Swetz, Henry S. Warren, Jr. | 2009-01-13 |
| 7454585 | Efficient and flexible memory copy operation | Ravi Kumar Arimilli, Rama K. Govindaraju, Bruce Mealey, Satya P. Sharma, Balaram Sinharoy | 2008-11-18 |
| 7203790 | Flexible techniques for associating cache memories with processors and main memory | Monty M. Denneau, Henry S. Warren, Jr. | 2007-04-10 |
| 6961782 | Methods for routing packets on a linear array of processors | Monty M. Denneau, Richard A. Swetz, Henry S. Warren, Jr. | 2005-11-01 |
| 6961804 | Flexible techniques for associating cache memories with processors and main memory | Monty M. Denneau, Henry S. Warren, Jr. | 2005-11-01 |
| 6384833 | Method and parallelizing geometric processing in a graphics rendering pipeline | Monty M. Denneau, Henry S. Warren, Jr. | 2002-05-07 |
| 5901326 | Memory bus address snooper logic for determining memory activity without performing memory accesses | Kevin J. Gildea, Peter K. Szwed | 1999-05-04 |
| 5805589 | Central shared queue based time multiplexed packet switch with deadlock avoidance | Monty M. Denneau | 1998-09-08 |
| 5600822 | Resource allocation synchronization in a parallel processing system | Donald G. Grice | 1997-02-04 |
| 5566342 | Scalable switch wiring technique for large arrays of processors | Monty M. Denneau, Donald G. Grice, Craig Brian Stunkel | 1996-10-15 |
| 5546391 | Central shared queue based time multiplexed packet switch with deadlock avoidance | Monty M. Denneau | 1996-08-13 |
| 5448558 | Method and apparatus for managing packet FIFOS | Kevin J. Gildea, Yun Huang | 1995-09-05 |