Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7467277 | Memory controller operating in a system with a variable system clock | Melissa Ann Barnum, Mark David Bellows, Lonny Lambrecht, Tolga Ozguner | 2008-12-16 |
| 7380052 | Reuse of functional data buffers for pattern buffers in XDR DRAM | Mark David Bellows, Kent Harold Haselhorst, Tolga Ozguner | 2008-05-27 |
| 7363442 | Separate handling of read and write of read-modify-write | Melissa Ann Barnum, Lonny Lambrecht | 2008-04-22 |
| 7321950 | Method and apparatus for managing write-to-read turnarounds in an early read after write memory system | Mark David Bellows, Kent Harold Haselhorst, Ryan Abel Heckendorf, Tolga Ozguner | 2008-01-22 |
| 7287103 | Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes | Kent Harold Haselhorst, Charles Ray Johns, Peichun Peter Liu | 2007-10-23 |
| 7272699 | Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs | Ryan Abel Heckendorf | 2007-09-18 |
| 7266650 | Method, apparatus, and computer program product for implementing enhanced circular queue using loop counts | Lonny Lambrecht | 2007-09-04 |
| 7248595 | Method, apparatus, and computer program product for implementing packet ordering | Kerry Christopher Imming, John D. Irish | 2007-07-24 |
| 7240166 | Method and apparatus for implementing packet work area accesses and buffer sharing | — | 2007-07-03 |
| 7225097 | Methods and apparatus for memory calibration | Brian M. McKevett, Tolga Ozguner | 2007-05-29 |
| 7089387 | Methods and apparatus for maintaining coherency in a multi-processor system | Kerry Christopher Imming, John D. Irish | 2006-08-08 |
| 6909315 | Data strobe signals (DQS) for high speed dynamic random access memories (DRAMs) | Michael Frank Carnevale, Daniel F. Moertl | 2005-06-21 |
| 6260164 | SRAM that can be clocked on either clock phase | Anthony Gus Aipperspach, Leland Leslie Day, Charles L. Johnson | 2001-07-10 |
| 6195775 | Boundary scan latch configuration for generalized scan designs | Steven M. Douskey, Daniel G. Young | 2001-02-27 |
| 6178534 | System and method for using LBIST to find critical paths in functional logic | Leland Leslie Day | 2001-01-23 |
| 6158032 | Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof | Guy Richard Currier, Leland Leslie Day, Steven M. Douskey, James Maurice Wallin | 2000-12-05 |
| 5835502 | Method and apparatus for handling variable data word widths and array depths in a serial shared abist scheme | Anthony Gus Aipperspach, Todd A. Christensen, Leland Leslie Day, Murali Vaddigiri, Paul Wong | 1998-11-10 |
| 5815694 | Apparatus and method to change a processor clock frequency | Charles L. Johnson, James D. Strom | 1998-09-29 |
| 5663966 | System and method for minimizing simultaneous switching during scan-based testing | Leland Leslie Day, Steven M. Douskey | 1997-09-02 |