Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9087612 | DRAM error detection, evaluation, and correction | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-07-21 |
| 9071277 | Correction of structured burst errors in data | Luis A. Lastras-Montano | 2015-06-30 |
| 9058896 | DRAM refresh | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras +1 more | 2015-06-16 |
| 9037930 | Managing errors in a DRAM by weak cell encoding | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2015-05-19 |
| 9001609 | Hybrid latch and fuse scheme for memory repair | Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano | 2015-04-07 |
| 8995217 | Hybrid latch and fuse scheme for memory repair | Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano | 2015-03-31 |
| 8897062 | Memory programming for a phase change memory cell | Matthew J. Breitwisch, Roger W. Cheek, Stefanie Chiras, Ibrahim M. Elfadel, John P. Karidis +3 more | 2014-11-25 |
| 8898544 | DRAM error detection, evaluation, and correction | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2014-11-25 |
| 8887014 | Managing errors in a DRAM by weak cell encoding | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano +1 more | 2014-11-11 |
| 8880834 | Low latency and persistent data storage | Blake G. Fitch, Ashish Jagmohan, Todd E. Takken | 2014-11-04 |
| 8874846 | Memory cell presetting for improved memory performance | Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano, Moinuddin K. Qureshi | 2014-10-28 |
| 8868978 | Reclaiming discarded solid state devices | Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma | 2014-10-21 |
| 8862944 | Isolation of faulty links in a transmission medium | John Steven Dodson, Frank D. Ferraiolo, Kevin C. Gower, Ashish Jagmohan, Luis A. Lastras-Montano +1 more | 2014-10-14 |
| 8861266 | Planar phase-change memory cell with parallel electrical paths | John P. Karidis | 2014-10-14 |
| 8848471 | Method for optimizing refresh rate for DRAM | Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras +1 more | 2014-09-30 |
| 8769374 | Multi-write endurance and error control coding of non-volatile memories | Ashish Jagmohan | 2014-07-01 |
| 8685785 | Planar phase-change memory cell with parallel electrical paths | John P. Karidis | 2014-04-01 |
| 8656130 | Low latency and persistent data storage | Blake G. Fitch, Ashish Jagmohan, Todd E. Takken | 2014-02-18 |
| 8656118 | Adaptive wear leveling via monitoring the properties of memory reference stream | John P. Karidis, Luis A. Lastras-Montano, Moinuddin K. Qureshi | 2014-02-18 |
| 8624217 | Planar phase-change memory cell with parallel electrical paths | John P. Karidis | 2014-01-07 |
| 8621328 | Wear-focusing of non-volatile memories for improved endurance | Ashish Jagmohan | 2013-12-31 |
| 8575008 | Post-fabrication self-aligned initialization of integrated devices | John P. Karidis | 2013-11-05 |
| 8560922 | Bad block management for flash memory | John A. Bivens, Ashish Jagmohan | 2013-10-15 |
| 8553474 | Increased capacity heterogeneous storage elements | Ibrahim M. Elfadel, Ashish Jagmohan, Luis A. Lastras-Montano, Mayank Sharma | 2013-10-08 |
| 8499221 | Accessing coded data stored in a non-volatile memory | Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano | 2013-07-30 |