Issued Patents All Time
Showing 626–650 of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9383930 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-07-05 |
| 9384133 | Synchronizing updates of page table status indicators and performing bulk operations | — | 2016-07-05 |
| 9384130 | Rewriting symbol address initialization sequences | Ulrich Weigand | 2016-07-05 |
| 9384000 | Caching optimized internal instructions in loop buffer | Valentina Salapura | 2016-07-05 |
| 9383996 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel | 2016-07-05 |
| 9378022 | Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching | Valentina Salapura | 2016-06-28 |
| 9372695 | Optimization of instruction groups across group boundaries | — | 2016-06-21 |
| 9372693 | Run-time instrumentation sampling in transactional-execution mode | Jonathan D. Bradbury, Charles W. Gainey, Jr. | 2016-06-21 |
| 9367316 | Run-time instrumentation indirect sampling by instruction operation code | Jonathan D. Bradbury, Charles W. Gainey, Jr., Eric M. Schwarz | 2016-06-14 |
| 9361041 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Maged M. Michael, Valentina Salapura +2 more | 2016-06-07 |
| 9361108 | Forming instruction groups based on decode time instruction optimization | — | 2016-06-07 |
| 9361144 | Predictive fetching and decoding for selected return instructions | Valentina Salapura | 2016-06-07 |
| 9361031 | Software indications and hints for coalescing memory transactions | Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum | 2016-06-07 |
| 9361146 | Predictive fetching and decoding for selected return instructions | Valentina Salapura | 2016-06-07 |
| 9355040 | Adjunct component to provide full virtualization using paravirtualized hypervisors | — | 2016-05-31 |
| 9354874 | Scalable decode-time instruction sequence optimization of dependent instructions | Valentina Salapura | 2016-05-31 |
| 9354885 | Selective suppression of instruction cache-related directory access | Valentina Salapura | 2016-05-31 |
| 9354888 | Performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching | Valentina Salapura | 2016-05-31 |
| 9354947 | Linking a function with dual entry points | Ulrich Weigand | 2016-05-31 |
| 9355032 | Supporting multiple types of guests by a hypervisor | — | 2016-05-31 |
| 9355033 | Supporting multiple types of guests by a hypervisor | — | 2016-05-31 |
| 9348757 | System supporting multiple partitions with differing translation formats | — | 2016-05-24 |
| 9348643 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-24 |
| 9348763 | Asymmetric co-existent address translation structure formats | Anthony J. Bybell, David D. Dukro, Bradly G. Frey | 2016-05-24 |
| 9348616 | Linking a function with dual entry points | Ulrich Weigand | 2016-05-24 |