Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5574294 | Vertical dual gate thin film transistor with self-aligned gates / offset drain | — | 1996-11-12 |
| 5573964 | Method of making thin film transistor with a self-aligned bottom gate using diffusion from a dopant source layer | Louis L. Hsu, Mary J. Saccamango | 1996-11-12 |
| 5516721 | Isolation structure using liquid phase oxide deposition | Carol Galli, Louis L. Hsu, Seiki Ogura | 1996-05-14 |
| 5395786 | Method of making a DRAM cell with trench capacitor | Louis L. Hsu, Sieki Ogura | 1995-03-07 |
| 5389559 | Method of forming integrated interconnect for very high density DRAMs | Chang-Ming Hsieh, Louis L. Hsu, Toshio Mii, Seiki Ogura | 1995-02-14 |
| 5384152 | Method for forming capacitors with roughened single crystal plates | Jack C. Chu, Louis L. Hsu, Toshio Mii, Scott R. Stiffler, Manu J. Tejwani +1 more | 1995-01-24 |
| 5384277 | Method for forming a DRAM trench cell capacitor having a strap connection | Louis L. Hsu, Toshio Mii, Seiki Ogura | 1995-01-24 |
| 5382832 | Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding | Taqi Nasser Buti, Louis L. Hsu, Rajiv V. Joshi | 1995-01-17 |
| 5376578 | Method of fabricating a semiconductor device with raised diffusions and isolation | Louis L. Hsu, Seiki Ogura | 1994-12-27 |
| 5369049 | DRAM cell having raised source, drain and isolation | Joyce Elizabeth Acocella, Louis L. Hsu, Seiki Ogura, Nivo Rovedo | 1994-11-29 |
| 5318663 | Method for thinning SOI films having improved thickness uniformity | Taqi Nasser Buti | 1994-06-07 |
| 5260233 | Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding | Taqi Nasser Buti, Louis L. Hsu, Rajiv V. Joshi | 1993-11-09 |
| 5245206 | Capacitors with roughened single crystal plates | Jack O. Chu, Louis L. Hsu, Toshio Mii, Scott R. Stiffler, Manu J. Tejwani +1 more | 1993-09-14 |
| 5241203 | Inverse T-gate FET transistor with lightly doped source and drain region | Louis L. Hsu, Seiki Ogura, Paul J. Tsang | 1993-08-31 |
| 5227333 | Local interconnection having a germanium layer | — | 1993-07-13 |
| 5120668 | Method of forming an inverse T-gate FET transistor | Louis L. Hsu, Seiki Ogura, Paul J. Tsang | 1992-06-09 |
| 4916083 | High performance sidewall emitter transistor | Michael D. Monkowski | 1990-04-10 |
| 4871630 | Mask using lithographic image size reduction | Nicholas J. Giammarco, Alexander Gimpelson, George A. Kaplita, Alexander D. Lopata, Anthony F. Scaduto | 1989-10-03 |
| 4847670 | High performance sidewall emitter transistor | Michael D. Monkowski | 1989-07-11 |
| 4707218 | Lithographic image size reduction | Nicholas J. Giammarco, Alexander Gimpelson, George A. Kaplita, Alexander D. Lopata, Anthony F. Scaduto | 1987-11-17 |
| 4654119 | Method for making submicron mask openings using sidewall and lift-off techniques | Robert K. Cook | 1987-03-31 |
| 4641170 | Self-aligned lateral bipolar transistors | Seiki Ogura, Jacob Riseman, Nivo Rovedo | 1987-02-03 |
| 4636834 | Submicron FET structure and method of making | — | 1987-01-13 |
| 4554728 | Simplified planarization process for polysilicon filled trenches | — | 1985-11-26 |
| 4551906 | Method for making self-aligned lateral bipolar transistors | Seiki Ogura, Jacob Riseman, Nivo Rovedo | 1985-11-12 |