Issued Patents All Time
Showing 76–87 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4546535 | Method of making submicron FET structure | — | 1985-10-15 |
| 4506435 | Method for forming recessed isolated regions | William A. Pliskin, Jacob Riseman | 1985-03-26 |
| 4498095 | Semiconductor structure with improved isolation between two layers of polycrystalline silicon | Paul L. Garbarino, Stanley R. Makarewicz | 1985-02-05 |
| 4437108 | Double polysilicon contact structure | James R. Gardiner, Stanley R. Makarewicz, Martin Revitz | 1984-03-13 |
| 4407058 | Method of making dense vertical FET's | Joseph J. Fatula, Jr., Paul L. Garbarino | 1983-10-04 |
| 4403394 | Formation of bit lines for ram device | Paul J. Tsang | 1983-09-13 |
| 4394406 | Double polysilicon contact structure and process | James R. Gardiner, Stanley R. Makarewicz, Martin Revitz | 1983-07-19 |
| 4354309 | Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon | James R. Gardiner, William A. Pliskin, Martin Revitz | 1982-10-19 |
| 4341009 | Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate | Robert F. Bartholomew, Paul L. Garbarino, James R. Gardiner, Martin Revitz | 1982-07-27 |
| 4251571 | Method for forming semiconductor structure with improved isolation between two layers of polycrystalline silicon | Paul L. Garbarino, Stanley R. Makarewicz | 1981-02-17 |
| 4249968 | Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers | James R. Gardiner, William A. Pliskin, Martin Revitz | 1981-02-10 |
| 4191603 | Making semiconductor structure with improved phosphosilicate glass isolation | Paul L. Garbarino, Martin Revitz | 1980-03-04 |