Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806699 | Circuits and methods for DFE with reduced area and power consumption | Byungsub Kim | 2017-10-31 |
| 9793913 | Single-flux-quantum probabilistic digitizer | Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky, Mark B. Ritter | 2017-10-17 |
| 9614532 | Single-flux-quantum probabilistic digitizer | Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky, Mark B. Ritter | 2017-04-04 |
| 9541935 | Passgate strength calibration techniques for voltage regulators | Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still | 2017-01-10 |
| 9531086 | Dynamic phased array tapering without phase recalibration | Bodhisatwa Sadhu, Alberto Valdes Garcia | 2016-12-27 |
| 9467313 | Continuous-time linear equalizer for high-speed receiving unit | Pier Andrea Francese, Yong Liu, Thomas H. Toifl | 2016-10-11 |
| 9444437 | Circuits and methods for DFE with reduced area and power consumption | Byungsub Kim | 2016-09-13 |
| 9369263 | Calibration of sampling phase and aperature errors in multi-phase sampling systems | Matthew B. Baecher, John F. Ewen, Gautam Gangasani, Mounir Meghelli, Matthew James Paschal +1 more | 2016-06-14 |
| 9335370 | On-chip test for integrated AC coupling capacitors | Eugene Atwood, Matthew B. Baecher, Stanislav Polonsky | 2016-05-10 |
| 9288085 | Continuous-time linear equalizer for high-speed receiving unit | Pier Andrea Francese, Yong Liu, Thomas H. Toifl | 2016-03-15 |
| 9231796 | Power aware equalization in a serial communications link | Hayden C. Cranford, Jr., Daniel M. Dreps, David W. Siljenberg | 2016-01-05 |
| 9008169 | Circuits and methods for DFE with reduced area and power consumption | Byungsub Kim | 2015-04-14 |
| 8981829 | Passgate strength calibration techniques for voltage regulators | Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still | 2015-03-17 |
| 8964826 | Time domain analog multiplication techniques for adjusting tap weights of feed-forward equalizers | Ankur Agrawal | 2015-02-24 |
| 8964825 | Analog signal current integrators with tunable peaking function | Troy J. Beukema | 2015-02-24 |
| 8941415 | Edge selection techniques for correcting clock duty cycle | Ankur Agrawal | 2015-01-27 |
| 8913655 | Feed-forward equalizer architectures | Ankur Agrawal, Daniel J. Friedman, Zeynep Toprak Deniz | 2014-12-16 |
| 8841893 | Dual-loop voltage regulator architecture with high DC accuracy and fast response time | Carrie E. Cox, Zeynep Toprak-Deniz, Daniel J. Friedman, Joseph A. Iadanza, Todd M. Rasmus | 2014-09-23 |
| 8779865 | Ultra-compact PLL with wide tuning range and low noise | Herschel A. Ainspan, Daniel J. Friedman, Ankush Goel, Alexander V. Rylyakov | 2014-07-15 |
| 8774228 | Timing recovery method and apparatus for an input/output bus with link redundancy | Timothy O. Dickson, Daniel J. Friedman, Yong Liu, Sergey V. Rylov | 2014-07-08 |
| 8755428 | Feed-forward equalizer architectures | Ankur Agrawal, Daniel J. Friedman, Zeynep Toprak Deniz | 2014-06-17 |
| 8755220 | Hybrid superconducting-magnetic memory cell and array | William J. Gallagher, Mark B. Ketchen | 2014-06-17 |
| 8704583 | Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier | Steven M. Clements, Sergey V. Rylov | 2014-04-22 |
| 8686764 | Edge selection techniques for correcting clock duty cycle | Ankur Agrawal | 2014-04-01 |
| 8681839 | Calibration of multiple parallel data communications lines for high skew conditions | Timothy O. Dickson, Frank D. Ferraiolo, Robert J. Reese, Michael B. Spear | 2014-03-25 |