Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7380221 | Method and system for reduction of and/or subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-05-27 |
| 7373624 | Method and system for performing target enlargement in the presence of constraints | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-05-13 |
| 7370292 | Method for incremental design reduction via iterative overapproximation and re-encoding strategies | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-05-06 |
| 7370298 | Method for heuristic preservation of critical inputs during sequential reparameterization | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2008-05-06 |
| 7367002 | Method and system for parametric reduction of sequential designs | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2008-04-29 |
| 7360185 | Design verification using sequential and combinational transformations | Jason Raymond Baumgarter, Robert L. Kanzelman, Viresh Paruthi | 2008-04-15 |
| 7360181 | Enhanced structural redundancy detection | Jason R. Baumgartner, Viresh Paruthi, Fadi Z. Zaraket | 2008-04-15 |
| 7356792 | Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-04-08 |
| 7350179 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2008-03-25 |
| 7350169 | Method and system for enhanced verification through structural target decomposition | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-03-25 |
| 7350166 | Method and system for reversing the effects of sequential reparameterization on traces | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2008-03-25 |
| 7343573 | Method and system for enhanced verification through binary decision diagram-based target decomposition | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-03-11 |
| 7340694 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-03-04 |
| 7322017 | Method for verification using reachability overapproximation | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2008-01-22 |
| 7315996 | Method and system for performing heuristic constraint simplification | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-01-01 |
| 7299432 | Method for preserving constraints during sequential reparameterization | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2007-11-20 |
| 7266795 | System and method for engine-controlled case splitting within multiple-engine based verification framework | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2007-09-04 |
| 7260799 | Exploiting suspected redundancy for enhanced design verification | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2007-08-21 |
| 7203915 | Method for retiming in the presence of verification constraints | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2007-04-10 |
| 7093218 | Incremental, assertion-based design verification | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2006-08-15 |
| 6993734 | Use of time step information in a design verification system | Jason R. Baumgartner, Viresh Paruthi, Mark A. Williams | 2006-01-31 |
| 6983435 | Integrated design verification and design simplification system | Jason R. Baumgartner, Viresh Paruthi | 2006-01-03 |