Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7882473 | Sequential equivalence checking for asynchronous verification | Jason R. Baumgartner, Yee Ja, Viresh Paruthi, Barinjato Ramanandray | 2011-02-01 |
| 7882470 | Method for heuristic preservation of critical inputs during sequential reparameterization | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2011-02-01 |
| 7882459 | Method and system for reduction of AND/OR subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-02-01 |
| 7856609 | Using constraints in design verification | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2010-12-21 |
| 7831937 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-11-09 |
| 7823093 | Method and system for reduction of and/or subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-10-26 |
| 7793242 | Method and system for performing heuristic constraint simplification | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-09-07 |
| 7788615 | Computer program product for verification using reachability overapproximation | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2010-08-31 |
| 7788616 | Method and system for performing heuristic constraint simplification | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-08-31 |
| 7779378 | Computer program product for extending incremental verification of circuit design to encompass verification restraints | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-08-17 |
| 7765514 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2010-07-27 |
| 7752593 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2010-07-06 |
| 7743353 | Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2010-06-22 |
| 7734452 | Method and system for performing ternary verification | Jason R. Baumgartner, Viresh Paruthi, Matyas A. Sustik | 2010-06-08 |
| 7689943 | Parametric reduction of sequential design | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2010-03-30 |
| 7600209 | Generating constraint preserving testcases in the presence of dead-end constraints | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2009-10-06 |
| 7552407 | Method and system for performing target enlargement in the presence of constraints | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2009-06-23 |
| 7509605 | Extending incremental verification of circuit design to encompass verification restraints | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2009-03-24 |
| 7478344 | Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2009-01-13 |
| 7475370 | System for verification using reachability overapproximation | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2009-01-06 |
| 7448005 | Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-11-04 |
| 7437690 | Method for predicate-based compositional minimization in a verification environment | Jason R. Baumgartner, Viresh Paruthi, Fadi A. Zaraket | 2008-10-14 |
| 7421669 | Using constraints in design verification | Jason R. Baumgartner, Viresh Paruthi, Jiazhao Xu | 2008-09-02 |
| 7398488 | Trace equivalence identification through structural isomorphism detection with on the fly logic writing | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-07-08 |
| 7380222 | Method and system for performing minimization of input count during structural netlist overapproximation | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2008-05-27 |