Issued Patents All Time
Showing 101–125 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9823926 | Vector element rotate and insert under mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Timothy J. Slegel | 2017-11-21 |
| 9817693 | Coherence protocol augmentation to indicate transaction status | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura +1 more | 2017-11-14 |
| 9804823 | Shift significand of decimal floating point data | Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh | 2017-10-31 |
| 9785435 | Floating point instruction with selectable comparison attributes | Jonathan D. Bradbury, Michael K. Gschwind, Silvia M. Mueller, Brett Olsson | 2017-10-10 |
| 9778932 | Vector generate mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Timothy J. Slegel | 2017-10-03 |
| 9772944 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2017-09-26 |
| 9772874 | Prioritization of transactions based on execution by transactional core with super core indicator | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2017-09-26 |
| 9772786 | Address probing for transaction | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2017-09-26 |
| 9772843 | Vector find element equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-09-26 |
| 9766829 | Address probing for transaction | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael +2 more | 2017-09-19 |
| 9766859 | Checksum adder | James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. | 2017-09-19 |
| 9766896 | Optimizing grouping of instructions | Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr. +1 more | 2017-09-19 |
| 9760397 | Interprocessor memory status communication | Dan F. Greiner, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-09-12 |
| 9760379 | Register comparison for operand store compare (OSC) prediction | David S. Hutton, Wen H. Li | 2017-09-12 |
| 9740615 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2017-08-22 |
| 9740614 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Jonathan D. Bradbury, Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2017-08-22 |
| 9740483 | Vector checksum instruction | Jonathan D. Bradbury | 2017-08-22 |
| 9740482 | Vector generate mask instruction | Jonathan D. Bradbury, Robert F. Enenkel, Timothy J. Slegel | 2017-08-22 |
| 9740616 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-08-22 |
| 9733938 | Vector checksum instruction | Jonathan D. Bradbury | 2017-08-15 |
| 9733936 | Multifunctional hexadecimal instruction form system and program product | Ronald M. Smith, Sr. | 2017-08-15 |
| 9727334 | Vector exception code | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-08-08 |
| 9720725 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-08-01 |
| 9715385 | Vector exception code | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-07-25 |
| 9715383 | Vector find element equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-07-25 |