ES

Eric M. Schwarz

IBM: 267 patents #95 of 70,183Top 1%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
AM AMD: 1 patents #5,683 of 9,279Top 65%
IS International Business Systems: 1 patents #1 of 22Top 5%
📍 Gardiner, NY: #1 of 33 inventorsTop 4%
🗺 New York: #70 of 115,490 inventorsTop 1%
Overall (All Time): #1,616 of 4,157,543Top 1%
273
Patents All Time

Issued Patents All Time

Showing 76–100 of 273 patents

Patent #TitleCo-InventorsDate
9971628 Salvaging hardware transactions Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura 2018-05-15
9971626 Coherence protocol augmentation to indicate transaction status Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Christian Jacobi, Valentina Salapura +1 more 2018-05-15
9959118 Instruction to load data up to a dynamically determined memory boundary Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel 2018-05-01
9959117 Instruction to load data up to a specified memory boundary indicated by the instruction Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel 2018-05-01
9952943 Salvaging hardware transactions Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura 2018-04-24
9952804 Hardware transaction transient conflict resolution Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more 2018-04-24
9946542 Instruction to load data up to a specified memory boundary indicated by the instruction Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel 2018-04-17
9946494 Hardware transaction transient conflict resolution Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more 2018-04-17
9940102 Partial stochastic rounding that includes sticky and guard bits Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky 2018-04-10
9928032 Checksum adder James R. Cuffney, John G. Rell, Jr., Patrick M. West, Jr. 2018-03-27
9928173 Conditional inclusion of data in a transactional memory read set Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-27
9921895 Transactional memory operations with read-only atomicity Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-20
9921872 Interprocessor memory status communication Dan F. Greiner, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-20
9921834 Prefetching of discontiguous storage locations in anticipation of transactional execution Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more 2018-03-20
9916180 Interprocessor memory status communication Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-13
9916179 Interprocessor memory status communication Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel 2018-03-13
9916159 Programmable linear feedback shift register Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky 2018-03-13
9880811 Reproducible stochastic rounding for out of order processors Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky 2018-01-30
9870254 Multithreaded transactions Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2018-01-16
9864692 Managing read tags in a transactional memory Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel 2018-01-09
9864690 Detecting cache conflicts by utilizing logical address comparisons in a transactional memory Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel 2018-01-09
9858074 Non-default instruction handling within transaction Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum 2018-01-02
9851946 Round for reround mode in a decimal floating point instruction Michael F. Cowlishaw, Ronald M. Smith, Sr., Phil C. Yeh 2017-12-26
9830159 Suspending branch prediction upon entering transactional execution mode Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum 2017-11-28
9823924 Vector element rotate and insert under mask instruction Jonathan D. Bradbury, Robert F. Enenkel, Timothy J. Slegel 2017-11-21