Issued Patents All Time
Showing 26–50 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10613861 | Programmable linear feedback shift register | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2020-04-07 |
| 10606638 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2020-03-31 |
| 10606589 | Vector checksum instruction | Jonathan D. Bradbury | 2020-03-31 |
| 10565117 | Instruction to cancel outstanding cache prefetches | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2020-02-18 |
| 10489152 | Stochastic rounding floating-point add instruction using entropy from a register | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2019-11-26 |
| 10489153 | Stochastic rounding floating-point add instruction using entropy from a register | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2019-11-26 |
| 10445066 | Stochastic rounding floating-point multiply instruction using entropy from a register | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2019-10-15 |
| 10423388 | Round for reround mode in a decimal floating point instruction | Michael F. Cowlishaw, Ronald M. Smith, Sr., Phil C. Yeh | 2019-09-24 |
| 10365927 | Non-default instruction handling within transaction | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2019-07-30 |
| 10365929 | Spin loop delay instruction | Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2019-07-30 |
| 10360153 | System operation queue for transaction | Jonathan D. Bradbury, Michael K. Gschwind | 2019-07-23 |
| 10353734 | Prioritization of transactions based on execution by transactional core with super core indicator | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2019-07-16 |
| 10346305 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2019-07-09 |
| 10331565 | Transactional memory system including cache versioning architecture to implement nested transactions | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2019-06-25 |
| 10318430 | System operation queue for transaction | Jonathan D. Bradbury, Michael K. Gschwind | 2019-06-11 |
| 10310855 | Non-default instruction handling within transaction | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2019-06-04 |
| 10303478 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Timothy J. Slegel | 2019-05-28 |
| 10296344 | Convert from zoned format to decimal floating point format | Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Timothy J. Slegel | 2019-05-21 |
| 10275254 | Spin loop delay instruction | Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2019-04-30 |
| 10275246 | Programmable linear feedback shift register | Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky | 2019-04-30 |
| 10270775 | Mechanism for creating friendly transactions with credentials | Jonathan D. Bradbury, Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2019-04-23 |
| 10270773 | Mechanism for creating friendly transactions with credentials | Jonathan D. Bradbury, Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2019-04-23 |
| 10261787 | Multifunctional hexadecimal instruction form system and program product | Ronald M. Smith, Sr. | 2019-04-16 |
| 10255189 | Mechanism for creating friendly transactions with credentials | Jonathan D. Bradbury, Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum | 2019-04-09 |
| 10241757 | Decimal shift and divide instruction | Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia M. Mueller | 2019-03-26 |