Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6286083 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Jeffrey C. Stevens +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, C. Kevin Coffee +1 more | 2001-08-21 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-08-07 |
| 6269433 | Memory controller using queue look-ahead to reduce memory latency | Phillip M. Jones | 2001-07-31 |
| 6249847 | Computer system with synchronous memory arbiter that permits asynchronous memory requests | Kenneth T. Chin, Phillip M. Jones, Robert A. Lester, Michael J. Collins | 2001-06-19 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Jeffrey C. Stevens +3 more | 2001-06-12 |
| 6233661 | Computer system with memory controller that hides the next cycle during the current cycle | Phillip M. Jones | 2001-05-15 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-04-10 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2000-12-12 |
| 6078338 | Accelerated graphics port programmable memory access arbiter | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert A. Lester | 2000-06-20 |
| 5517646 | Expansion device configuration system having two configuration modes which uses automatic expansion configuration sequence during first mode and configures the device individually during second mode | Mark W. Welker, John S. Thayer | 1996-05-14 |