Issued Patents All Time
Showing 201–225 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6271084 | Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process | Yeur-Luen Tu, Chia-Shiung Tsai | 2001-08-07 |
| 6262447 | Single polysilicon DRAM cell and array with current gain | — | 2001-07-17 |
| 6255713 | Current source using merged vertical bipolar transistor based on gate induced gate leakage current | — | 2001-07-03 |
| 6240015 | Method for reading 2-bit ETOX cells using gate induced drain leakage current | Dahcheng Lin | 2001-05-29 |
| 6200852 | Method to fabricate DRAM capacitor | Chine-Gie Lou | 2001-03-13 |
| 6184548 | DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor | George Meng-Jaw Cherng | 2001-02-06 |
| 6181601 | Flash memory cell using p+/N-well diode with double poly floating gate | — | 2001-01-30 |
| 6174770 | Method for forming a crown capacitor having HSG for DRAM memory | — | 2001-01-16 |
| 6174767 | Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise | — | 2001-01-16 |
| 6175605 | Edge triggered delay line, a multiple adjustable delay line circuit, and an application of same | — | 2001-01-16 |
| 6171923 | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor | Chih-Yuan Lu | 2001-01-09 |
| 6163482 | One transistor EEPROM cell using ferro-electric spacer | — | 2000-12-19 |
| 6160286 | Method for operation of a flash memory using n+/p-well diode | — | 2000-12-12 |
| 6144075 | CMOS inverter using gate induced drain leakage current | — | 2000-11-07 |
| 6143607 | Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current | — | 2000-11-07 |
| 6136635 | Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region | Albert Bergemont | 2000-10-24 |
| 6133780 | Digitally tunable voltage reference using a neuron MOSFET | — | 2000-10-17 |
| 6133604 | NOR array architecture and operation methods for ETOX cells capable of full EEPROM functions | — | 2000-10-17 |
| 6111788 | Method for programming and erasing a triple-poly split-gate flash | Chih-Ming Chen | 2000-08-29 |
| 6111286 | Low voltage low power n-channel flash memory cell using gate induced drain leakage current | Chih-Ming Chen | 2000-08-29 |
| 6111925 | Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time | — | 2000-08-29 |
| 6091635 | Electron injection method for substrate-hot-electron program and erase V.sub.T tightening for ETOX cell | Chih-Ming Chen | 2000-07-18 |
| 6088058 | Capacitive coupled bipolar active pixel imager having overflow protection and electronic shutter | Carver A. Mead, Tobi Delbruck | 2000-07-11 |
| 6087690 | Single polysilicon DRAM cell with current gain | — | 2000-07-11 |
| 6088259 | SRAM cell using two single transistor inverters | — | 2000-07-11 |