Issued Patents All Time
Showing 151–175 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8435802 | Conductor layout technique to reduce stress-induced void formations | Tai-Chun Huang, Chih-Hsiang Yao | 2013-05-07 |
| 8421166 | Semiconductor device and fabrication thereof | Wen-Chuan Chiang, Mu-Chi Chiang, Cheng-Ku Chen | 2013-04-16 |
| 8362528 | Logic switch and circuits utilizing the switch | — | 2013-01-29 |
| 8273639 | Atomic layer deposition method and semiconductor device formed by the same | Hua Ji, Fumitake Mieno | 2012-09-25 |
| 8264863 | Green transistor for nano-Si ferro-electric RAM and method of operating the same | Deyuan Xiao | 2012-09-11 |
| 8208286 | Green transistor for resistive random access memory and method of operating the same | Deyuan Xiao | 2012-06-26 |
| 8158512 | Atomic layer deposition method and semiconductor device formed by the same | Hua Ji, Fumitake Mieno, Sean Zhang | 2012-04-17 |
| 7994040 | Semiconductor device and fabrication thereof | Wen-Chuan Chiang, Mu-Chi Chiang, Chang-Ku Chen | 2011-08-09 |
| 7804155 | Vertical resistors | — | 2010-09-28 |
| 7737532 | Hybrid Schottky source-drain CMOS for high mobility and low barrier | Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee | 2010-06-15 |
| 7709386 | Atomic layer deposition method and semiconductor device formed by the same | Hua Ji, Fumitake Mieno | 2010-05-04 |
| 7635882 | Logic switch and circuits utilizing the switch | — | 2009-12-22 |
| 7633110 | Memory cell | Wen-Chuan Chiang, Cheng-Ku Chen | 2009-12-15 |
| 7589387 | SONOS type two-bit FinFET flash memory cell | Jiunn-Ren Hwang, Fu-Liang Yang | 2009-09-15 |
| 7564105 | Quasi-plannar and FinFET-like transistors on bulk silicon | Wen-Chuan Chiang, Mu-Chi Chiang | 2009-07-21 |
| 7498657 | Vertical resistors and band-gap voltage reference circuits | — | 2009-03-03 |
| 7371634 | Amorphous carbon contact film for contact hole etch process | Wen-Chuan Chiang, Cheng-Ku Chen, Mu-Chi Chiang | 2008-05-13 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control | — | 2008-01-22 |
| 7291553 | Method for forming dual damascene with improved etch profiles | Cheng-Ku Chen | 2007-11-06 |
| 7176537 | High performance CMOS with metal-gate and Schottky source/drain | Wen-Chin Lee, Chung-Hu Ke | 2007-02-13 |
| 7129140 | Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing | Cheng-Ku Chen | 2006-10-31 |
| 7106088 | Method of predicting high-k semiconductor device lifetime | Ching-Wei Tsai, Chih-Hao Wang | 2006-09-12 |
| 7081395 | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials | Yee-Chia Yeo, Chenming Hu | 2006-07-25 |
| 7078766 | Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents | — | 2006-07-18 |
| 7018886 | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control | — | 2006-03-28 |