Issued Patents All Time
Showing 176–200 of 273 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7002213 | Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents | — | 2006-02-21 |
| 6949471 | Method for fabricating poly patterns | Ching-Chen Hao, Hung-Jen Lin, Chih-Heng Shen | 2005-09-27 |
| 6943391 | Modification of carrier mobility in a semiconductor device | Wai-Yi Lien | 2005-09-13 |
| 6905929 | Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process | Richard B. Merrill, Albert Bergemont | 2005-06-14 |
| 6885068 | Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation | — | 2005-04-26 |
| 6855587 | Gate-controlled, negative resistance diode device using band-to-band tunneling | — | 2005-02-15 |
| 6828211 | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control | — | 2004-12-07 |
| 6822283 | Low temperature MIM capacitor for mixed-signal/RF applications | Dahcheng Lin | 2004-11-23 |
| 6759699 | Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation | — | 2004-07-06 |
| 6670279 | Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers | Chih-Yang Pai, Bi-Ling Chen | 2003-12-30 |
| 6657240 | Gate-controlled, negative resistance diode device using band-to-band tunneling | — | 2003-12-02 |
| 6579791 | Method to form dual damascene structure | Yeur-Luen Tu, Chia-Shiung Tsai | 2003-06-17 |
| 6555442 | Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer | Chih-Yang Pai, Chih-Hsing Yu, Yeur-Luen Tu, Chia-Shiung Tsai | 2003-04-29 |
| 6552397 | Charge pump device formed on silicon-on-insulator and operation method | — | 2003-04-22 |
| 6528366 | Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications | Yeur-Luen Tu, Dah-Chih Lin | 2003-03-04 |
| 6509606 | Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process | Richard B. Merrill, Albert Bergemont | 2003-01-21 |
| 6501120 | Capacitor under bitline (CUB) memory cell structure employing air gap void isolation | Yeur-Luen Tu, Chia-Shiung Tsai | 2002-12-31 |
| 6501109 | Active CMOS pixel with exponential output based on the GIDL mechanism | — | 2002-12-31 |
| 6500706 | Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM | — | 2002-12-31 |
| 6486025 | Methods for forming memory cell structures | Yuan-Hung Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Chih-Hsing Yu | 2002-11-26 |
| 6486529 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Chia-Shiung Tsai, Yeur-Luen Tu | 2002-11-26 |
| 6373090 | Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise | — | 2002-04-16 |
| 6362012 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Chia-Shiung Tsai, Yeur-Luen Tu | 2002-03-26 |
| 6288943 | Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate | — | 2001-09-11 |
| 6281550 | Transistor and logic circuit of thin silicon-on-insulator wafers based on gate induced drain leakage currents | — | 2001-08-28 |