Issued Patents All Time
Showing 126–150 of 302 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7958173 | Population count approximation circuit and method thereof | Kelly K. Taylor | 2011-06-07 |
| 7937573 | Metric for selective branch target buffer (BTB) allocation | Jeffrey W. Scott | 2011-05-03 |
| 7931190 | Circuit and method for correlated inputs to a population count circuit | Kelly K. Taylor | 2011-04-26 |
| 7925862 | Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges | Kevin B. Traylor | 2011-04-12 |
| 7895422 | Selective postponement of branch target buffer (BTB) allocation | Jeffrey W. Scott | 2011-02-22 |
| 7873819 | Branch target buffer addressing in a data processor | Jeffrey W. Scott | 2011-01-18 |
| 7870434 | Method and apparatus for masking debug resources | Alistair Robertson, Jimmy Gumulja | 2011-01-11 |
| 7870430 | Method and apparatus for sharing debug resources | Alistair Robertson, Ray Marshall | 2011-01-11 |
| 7870400 | System having a memory voltage controller which varies an operating voltage of a memory and method therefor | Prashant U. Kenkare | 2011-01-11 |
| 7865897 | Selective transaction request processing at an interconnect during a lockout | Benjamin C. Eckermann, Brett Murdock | 2011-01-04 |
| 7865704 | Selective instruction breakpoint generation based on a count of instruction source events | — | 2011-01-04 |
| 7853834 | Instruction-based timer control during debug | Jason T. Nearing | 2010-12-14 |
| 7831818 | Exception-based timer control | — | 2010-11-09 |
| 7831862 | Selective timer control during single-step instruction execution | Jason T. Nearing | 2010-11-09 |
| 7823033 | Data processing with configurable registers | Jimmy Gumulja | 2010-10-26 |
| 7814300 | Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access | Jeffrey W. Scott | 2010-10-12 |
| 7805590 | Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence | Kevin B. Traylor | 2010-09-28 |
| 7802038 | Communication steering for use in a multi-master shared resource system | Ryan D. Bedwell, Arnold R. Cruz, John J. Vaglica | 2010-09-21 |
| 7800974 | Adjustable pipeline in a memory circuit | Shayan Zhang, Huy B. Nguyen | 2010-09-21 |
| 7734898 | System and method for specifying an immediate value in an instruction | — | 2010-06-08 |
| 7689815 | Debug instruction for use in a data processing system | Michael D. Snyder, Gary L. Whisenhunt | 2010-03-30 |
| 7681078 | Debugging a processor through a reset event | — | 2010-03-16 |
| 7668029 | Memory having sense time of variable duration | Perry H. Pelley | 2010-02-23 |
| 7638903 | Power supply selection for multiple circuits on an integrated circuit | Perry H. Pelley | 2009-12-29 |
| 7627795 | Pipelined data processor with deterministic signature generation | Jimmy Gumulja | 2009-12-01 |