Issued Patents All Time
Showing 76–100 of 302 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8578384 | Method and apparatus for activating system components | Shayan Zhang | 2013-11-05 |
| 8572345 | Memory management unit (MMU) having region descriptor globalization controls and method of operation | — | 2013-10-29 |
| 8572147 | Method for implementing a bit-reversed increment in a data processing system | — | 2013-10-29 |
| 8566836 | Multi-core system on chip | Ravindraraj Ramaraju, David R. Bearden | 2013-10-22 |
| 8566672 | Selective checkbit modification for error correction | Joseph C. Circello | 2013-10-22 |
| 8533400 | Selective memory access to different local memory ports and method thereof | — | 2013-09-10 |
| 8504777 | Data processor for processing decorated instructions with cache bypass | — | 2013-08-06 |
| 8438547 | Address translation trace message generation for debug | Richard G. Collins | 2013-05-07 |
| 8423721 | Cache coherency protocol in a data processing system | — | 2013-04-16 |
| 8407457 | System and method for monitoring debug events | — | 2013-03-26 |
| 8402258 | Debug message generation using a selected address type | — | 2013-03-19 |
| 8386747 | Processor and method for dynamic and selective alteration of address translation | James B. Eifert | 2013-02-26 |
| 8364896 | Method and apparatus for configuring a unified cache based on an associated error rate | — | 2013-01-29 |
| 8364937 | Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor | Jeffrey W. Scott | 2013-01-29 |
| 8356239 | Selective cache way mirroring | — | 2013-01-15 |
| 8327082 | Snoop request arbitration in a data processing system | Quyen Pho | 2012-12-04 |
| 8316186 | Method and apparatus for managing cache reliability based on an associated error rate | — | 2012-11-20 |
| 8307196 | Data processing system having bit exact instructions and methods therefor | Imran Ahmed, Dan E. Tamir | 2012-11-06 |
| 8291305 | Error detection schemes for a cache in a data processing system | Quyen Pho, Michael J. Rochford | 2012-10-16 |
| 8275977 | Debug signaling in a multiple processor data processing system | Jimmy Gumulja | 2012-09-25 |
| 8266498 | Implementation of multiple error detection schemes for a cache | — | 2012-09-11 |
| 8261047 | Qualification of conditional debug instructions based on address | Michael D. Snyder, Gary L. Whisenhunt | 2012-09-04 |
| 8254161 | Device that can be rendered useless and method thereof | Kenneth R. Burch | 2012-08-28 |
| 8255748 | Soft error and transient error detection device and methods therefor | Troy L. Cooper | 2012-08-28 |
| 8205068 | Branch target buffer allocation | Jeffrey W. Scott | 2012-06-19 |