Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5802272 | Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system | Sharon E. Perl, G. Michael Uhler, David G. Conroy | 1998-09-01 |
| 5796939 | High frequency sampling of processor performance counters | Lance M. Berc, Sanjay Ghemawat, Monika H. Henzinger, Carl A. Waldspurger, William E. Weihl | 1998-08-18 |
| 5778423 | Prefetch instruction for improving performance in reduced instruction set processor | Richard T. Witek | 1998-07-07 |
| 5764885 | Apparatus and method for tracing data flows in high-speed computer systems | Sharon E. Perl, G. Michael Uhler, David G. Conroy | 1998-06-09 |
| 5652889 | Alternate execution and interpretation of computer program having code at unknown locations due to transfer instructions having computed destination addresses | — | 1997-07-29 |
| 5649203 | Translating, executing, and re-translating a computer program for finding and translating program code at unknown program addresses | — | 1997-07-15 |
| 5636366 | System and method for preserving instruction state-atomicity for translated program | Scott Robinson, Richard T. Witek | 1997-06-03 |
| 5568624 | Byte-compare operation for high-performance processor | Richard T. Witek | 1996-10-22 |
| 5507030 | Successive translation, execution and interpretation of computer program having code at unknown locations due to execution transfer instructions having computed destination addresses | — | 1996-04-09 |
| 5469551 | Method and apparatus for eliminating branches using conditional move instructions | Richard T. Witek | 1995-11-21 |
| 5454091 | Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed | Richard T. Witek | 1995-09-26 |
| 5450575 | Use of stack depth to identify machine code mistakes | — | 1995-09-12 |
| 5450349 | Computer system performance evaluation system and method | John F. Brown, G. Michael Uhler | 1995-09-12 |
| 5442571 | Method and apparatus for cache miss reduction by simulating cache associativity | — | 1995-08-15 |
| 5428786 | Branch resolution via backward symbolic execution | — | 1995-06-27 |
| 5410682 | In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor | Richard T. Witek | 1995-04-25 |
| 5367705 | In-register data manipulation using data shift in reduced instruction set processor | Richard T. Witek | 1994-11-22 |
| 5317740 | Alternate and iterative analysis of computer programs for locating translatable code by resolving callbacks and other conflicting mutual dependencies | — | 1994-05-31 |
| 5307504 | System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events | Scott Robinson | 1994-04-26 |
| 5287490 | Identifying plausible variable length machine code of selecting address in numerical sequence, decoding code strings, and following execution transfer paths | — | 1994-02-15 |
| 5276809 | Method and apparatus for capturing real-time data bus cycles in a data processing system | Lawrence A. P. Chisvin, John K. Grooms, Donald W. Smelser | 1994-01-04 |
| 5193167 | Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system | Richard T. Witek | 1993-03-09 |
| 5155843 | Error transition mode for multi-processor system | Rebecca L. Stamm, R. Iris Bahar, Michael A. Callander, Linda Chao, Derrick R. Meyer +3 more | 1992-10-13 |
| 5014195 | Configurable set associative cache with decoded data element enable lines | James Arthur Farrell | 1991-05-07 |
| 4982360 | Memory subsystem | William N. Johnson, Le Trong Nguyen, Stanley A. Lackey, Jr. | 1991-01-01 |