Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10600903 | Semiconductor device including a power transistor device and bypass diode | Edward Robert Van Brunt, Lin Cheng | 2020-03-24 |
| 10217824 | Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion implantation into silicon carbide using channeling | Alexander V. Suvorov | 2019-02-26 |
| 10134834 | Field effect transistor devices with buried well protection regions | Lin Cheng, Anant Agarwal, John Williams Palmour | 2018-11-20 |
| 10103230 | Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions | Edward Robert Van Brunt, Alexander V. Suvorov, Lin Cheng | 2018-10-16 |
| 9972677 | Methods of forming power semiconductor devices having superjunction structures with pillars having implanted sidewalls | Edward Robert Van Brunt, Lin Cheng, Daniel Jenner Lichtenwalner | 2018-05-15 |
| 9768259 | Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion implantation into silicon carbide using channeling | Alexander V. Suvorov | 2017-09-19 |
| 9741842 | Vertical power transistor device | Anant Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour | 2017-08-22 |
| 9570585 | Field effect transistor devices with buried well protection regions | Lin Cheng, Anant Agarwal, John Williams Palmour | 2017-02-14 |
| 9515199 | Power semiconductor devices having superjunction structures with implanted sidewalls | Edward Robert Van Brunt, Lin Cheng, Daniel Jenner Lichtenwalner | 2016-12-06 |
| 9484413 | Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions | Edward Robert Van Brunt, Alexander V. Suvorov, Lin Cheng | 2016-11-01 |
| 9425265 | Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure | Edward Robert Van Brunt, Lin Cheng, Anant Agarwal | 2016-08-23 |
| 9331197 | Vertical power transistor device | Anant Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour | 2016-05-03 |
| 9318597 | Layout configurations for integrating schottky contacts into a power transistor device | Edward Robert Van Brunt, Lin Cheng, John Williams Palmour | 2016-04-19 |
| 9306061 | Field effect transistor devices with protective regions | Lin Cheng, Anant Agarwal, John Williams Palmour | 2016-04-05 |
| 9236433 | Semiconductor devices in SiC using vias through N-type substrate for backside contact to P-type layer | Edward Robert Van Brunt, Daniel Jenner Lichtenwalner, Lin Cheng, Anant Agarwal, John Williams Palmour | 2016-01-12 |
| 9142668 | Field effect transistor devices with buried well protection regions | Lin Cheng, Anant Agarwal, John Williams Palmour | 2015-09-22 |
| 9111919 | Field effect device with enhanced gate dielectric structure | Daniel Jenner Lichtenwalner, Anant Agarwal, Lin Cheng, John Williams Palmour | 2015-08-18 |
| 9064738 | Methods of forming junction termination extension edge terminations for high power semiconductor devices and related semiconductor devices | Edward Robert Van Brunt, Lin Cheng, Anant Agarwal | 2015-06-23 |