Issued Patents All Time
Showing 101–125 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6541327 | Method to form self-aligned source/drain CMOS device on insulated staircase oxide | Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2003-04-01 |
| 6511884 | Method to form and/or isolate vertical transistors | Elgin Quek, Ravi Sundaresan, Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2003-01-28 |
| 6498386 | Cylindrical semiconductor capacitor | — | 2002-12-24 |
| 6468877 | Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2002-10-22 |
| 6461887 | Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan +2 more | 2002-10-08 |
| 6461900 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, James Lee Yong Meng, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2002-10-08 |
| 6455377 | Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee +2 more | 2002-09-24 |
| 6451706 | Attenuation of reflecting lights by surface treatment | Ron Fu Chu, Qun Ying Lin, Mei Sheng Zhou | 2002-09-17 |
| 6440800 | Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-08-27 |
| 6436774 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-08-20 |
| 6436770 | Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2002-08-20 |
| 6417056 | Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge | Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-07-09 |
| 6417054 | Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide | Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee +2 more | 2002-07-09 |
| 6406945 | Method for forming a transistor gate dielectric with high-K and low-K regions | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2002-06-18 |
| 6403485 | Method to form a low parasitic capacitance pseudo-SOI CMOS device | Elgin Quek, Ravi Sundaresan, James Lee Yong Meng, Ying Keung, Yelehanka Ramachandramurthy Pradeep +2 more | 2002-06-11 |
| 6380506 | Use of hot carrier effects to trim analog transistor pair | — | 2002-04-30 |
| 6380088 | Method to form a recessed source drain on a trench side wall with a replacement gate technique | Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2002-04-30 |
| 6354781 | Semiconductor manufacturing system | — | 2002-03-12 |
| 6313034 | Method for forming integrated circuit device structures from semiconductor substrate oxidation mask layers | Che-Chia Wei | 2001-11-06 |
| 6313008 | Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon | Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek +2 more | 2001-11-06 |
| 6306715 | Method to form smaller channel with CMOS device by isotropic etching of the gate materials | Lap Chan, Elgin Quek, Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung +2 more | 2001-10-23 |
| 6306714 | Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide | James Yongmeng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2001-10-23 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2001-10-16 |
| 6300177 | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials | Ravi Sundaresan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2001-10-09 |
| 6300653 | Method for forming a high areal capacitance planar capacitor | — | 2001-10-09 |