Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6387784 | Method to reduce polysilicon depletion in MOS transistors | Yung Fu Chong, Lap Chan, Kin Leong Pey | 2002-05-14 |
| 6387747 | Method to fabricate RF inductors with minimum area | Tae Jong Lee, Alex See, Lap Chan, Chua Chee Tee | 2002-05-14 |
| 6384437 | Low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Kheng Chok Tee, Lap Chan | 2002-05-07 |
| 6376360 | Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers | Tae Jong Lee | 2002-04-23 |
| 6355563 | Versatile copper-wiring layout design with low-k dielectric integration | Alex See, Yeow Kheng Lim, Tae Jong Lee, Lap Chan | 2002-03-12 |
| 6348385 | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant | Tae Jong Lee, Alex See, Lap Chan, Chee Tee Chua | 2002-02-19 |
| 6319772 | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | Kheng Chok Tee, Lap Chan | 2001-11-20 |
| 6319767 | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique | Tae Jong Lee, Alex See, Lap Chan, Yeow Kheng Lim | 2001-11-20 |
| 6284590 | Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors | Cheng Yeow Ng, Shao-fu Sanford Chu, Tae Jong Lee, Chua Chee Tee | 2001-09-04 |
| 6284610 | Method to reduce compressive stress in the silicon substrate during silicidation | Chee Tee Chua, Kin Leong Pey, Lap Chan | 2001-09-04 |