Issued Patents All Time
Showing 26–50 of 139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670242 | Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer | David C. Brady, Yi Ma | 2003-12-30 |
| 6664800 | Non-contact method for determining quality of semiconductor dielectrics | Carlos M. Chacon, Sundar Srinivasan Chetlur | 2003-12-16 |
| 6659846 | Pad for chemical mechanical polishing | Sudhanshu Misra | 2003-12-09 |
| 6616965 | Non-hydrolytic-sol-gel process for high K dielectric | Sudhanshu Misra | 2003-09-09 |
| 6605529 | Method of creating hydrogen isotope reservoirs in a semiconductor device | Sundar Srinivasan Chetlur, Jennifer M. McKinley, Minesh Patel, Jonathan Zhou | 2003-08-12 |
| 6599837 | Chemical mechanical polishing composition and method of polishing metal layers using same | Sailesh Mansinh Merchant, Sudhanshu Misra | 2003-07-29 |
| 6576522 | Methods for deuterium sintering | Sundar Srinivasan Chetlur, Minesh Patel, Sidhartha Sen, Vivek Saxena | 2003-06-10 |
| 6552381 | Trench capacitors in SOI substrates | Sailesh Chittipeddi, Charles Walter Pearce | 2003-04-22 |
| 6551946 | TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE | Yuanning Chen, Sundar Srinivasan Chetlur | 2003-04-22 |
| 6548422 | Method and structure for oxide/silicon nitride interface substructure improvements | David C. Brady, Carlos M. Chacon | 2003-04-15 |
| 6548854 | Compound, high-K, gate and capacitor insulator layer | Isik C. Kizilyalli, Yi Ma | 2003-04-15 |
| 6544107 | Composite polishing pads for chemical-mechanical polishing | Sudhanshu Misra | 2003-04-08 |
| 6541394 | Method of making a graded grown, high quality oxide layer for a semiconductor device | Yuanning Chen, Sailesh Mansinh Merchant | 2003-04-01 |
| 6540974 | Process for making mixed metal oxides | Sudhanshu Misra | 2003-04-01 |
| 6535014 | Electrical parameter tester having decoupling means | Sundar Srinivasan Chetlur | 2003-03-18 |
| 6524957 | Method of forming in-situ electroplated oxide passivating film for corrosion inhibition | Sailesh Mansinh Merchant, Sudhanshu Misra | 2003-02-25 |
| 6495875 | Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby | Siddhartha Bhowmik, Sailesh Mansinh Merchant, Sidhartha Sen | 2002-12-17 |
| 6492712 | High quality oxide for use in integrated circuits | Yuanning Chen, Sundar Srinivasan Chetlur, Sailesh Mansinh Merchant | 2002-12-10 |
| 6471925 | Method for treating an effluent gas during semiconductor processing | Sailesh Mansinh Merchant, Sudhanshu Misra | 2002-10-29 |
| 6461225 | Local area alloying for preventing dishing of copper during chemical-mechanical polishing (CMP) | Sudhanshu Misra | 2002-10-08 |
| 6458016 | Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method | Sailesh Mansinh Merchant, Sudhanshu Misra, Hem M. Vaidya | 2002-10-01 |
| 6458289 | CMP slurry for polishing semiconductor wafers and related methods | Sailesh Mansinh Merchant, Sudhanshu Misra | 2002-10-01 |
| 6439972 | Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method | Sudhanshu Misra, Sundar Chetlur, Vivek Saxena | 2002-08-27 |
| 6440829 | N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure | Yi Ma, Michael Laughery | 2002-08-27 |
| 6440849 | Microstructure control of copper interconnects | Sailesh Mansinh Merchant | 2002-08-27 |