Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840337 | Method for making a FINFET having reduced contact resistance | Hideki Takeuchi, Daniel J. Connelly, Marek Hytha, Richard Burton | 2020-11-17 |
| 10825901 | Semiconductor devices including hyper-abrupt junction region including a superlattice | Richard Burton, Marek Hytha | 2020-11-03 |
| 10825902 | Varactor with hyper-abrupt junction region including spaced-apart superlattices | Richard Burton, Marek Hytha | 2020-11-03 |
| 10818755 | Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Marek Hytha, Richard Burton | 2020-10-27 |
| 10811498 | Method for making superlattice structures with reduced defect densities | Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert John Stephenson | 2020-10-20 |
| 10777451 | Semiconductor device including enhanced contact structures having a superlattice | Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more | 2020-09-15 |
| 10741436 | Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface | Robert John Stephenson, Scott A. Kreps, Kalipatnam Vivek Rao | 2020-08-11 |
| 10727049 | Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice | Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert John Stephenson | 2020-07-28 |
| 10593761 | Method for making a semiconductor device having reduced contact resistance | Hideki Takeuchi, Daniel J. Connelly, Marek Hytha, Richard Burton | 2020-03-17 |
| 10580867 | FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Marek Hytha, Richard Burton | 2020-03-03 |
| 10580866 | Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance | Hideki Takeuchi, Daniel J. Connelly, Marek Hytha, Richard Burton | 2020-03-03 |
| 10566191 | Semiconductor device including superlattice structures with reduced defect densities | Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert John Stephenson | 2020-02-18 |
| 10468245 | Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice | Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert John Stephenson | 2019-11-05 |
| 10453945 | Semiconductor device including resonant tunneling diode structure having a superlattice | Hideki Takeuchi, Marek Hytha | 2019-10-22 |
| 10361243 | Method for making CMOS image sensor including superlattice to enhance infrared light absorption | Marek Hytha | 2019-07-23 |
| 10276625 | CMOS image sensor including superlattice to enhance infrared light absorption | Marek Hytha | 2019-04-30 |
| 10249745 | Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice | Hideki Takeuchi, Marek Hytha | 2019-04-02 |
| 10170560 | Semiconductor devices with enhanced deterministic doping and related methods | — | 2019-01-01 |
| 10170603 | Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers | Hideki Takeuchi, Marek Hytha | 2019-01-01 |
| 10170604 | Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers | Hideki Takeuchi, Marek Hytha | 2019-01-01 |
| 10109479 | Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice | Robert John Stephenson, Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha | 2018-10-23 |
| 10084045 | Semiconductor device including a superlattice and replacement metal gate structure and related methods | Tsu-Jae King Liu, Hideki Takeuchi | 2018-09-25 |
| 9972685 | Vertical semiconductor devices including superlattice punch through stop layer and related methods | Hideki Takeuchi, Erwin Trautmann | 2018-05-15 |
| 9941359 | Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods | Hideki Takeuchi | 2018-04-10 |
| 9899479 | Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods | Hideki Takeuchi | 2018-02-20 |