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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
ET

Erwin Trautmann — 7 Patents

AIAtomera Incorporated: 6 patents #12 of 20Top 60%
MTMears Technologies: 1 patents #11 of 14Top 80%
San Jose, CA: #8,545 of 32,062 inventorsTop 30%
California: #83,669 of 386,348 inventorsTop 25%
Overall (All Time): #680,018 of 4,157,543Top 20%
7 Patents All Time
Erwin Trautmann has been granted 7 US patents while listed as an inventor at Atomera Incorporated. The first was granted in 2016 and the most recent in May 2023. Erwin Trautmann ranks #680,018 of 4,157,543 US inventors in our database (top 16.4%). Patent records list Erwin Trautmann in San Jose, CA, US.

Patents per Year

Patents granted per year, 2016 to 2023Bar chart with a peak of 2 patents in 2016.peak 22016: 2 patents20162018: 1 patents20182020: 2 patents20202022: 1 patents20222023: 1 patents2023

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11664427 Vertical semiconductor device with enhanced contact structure and associated methods Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2023-05-30 $1,904,000
11387325 Vertical semiconductor device with enhanced contact structure and associated methods Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2022-07-12 $4,591,000
10879356 Method for making a semiconductor device including enhanced contact structures having a superlattice Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2020-12-29 $3,389,000
10777451 Semiconductor device including enhanced contact structures having a superlattice Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2020-09-15 $4,167,000
9972685 Vertical semiconductor devices including superlattice punch through stop layer and related methods Robert J. Mears, Hideki Takeuchi 2018-05-15 $1,469,000
9406753 Semiconductor devices including superlattice depletion layer stack and related methods Robert J. Mears, Hideki Takeuchi 2016-08-02
9275996 Vertical semiconductor devices including superlattice punch through stop layer and related methods Robert J. Mears, Hideki Takeuchi 2016-03-01