ET

Erwin Trautmann

AI Atomera Incorporated: 6 patents #12 of 20Top 60%
MT Mears Technologies: 1 patents #11 of 14Top 80%
📍 San Jose, CA: #8,424 of 32,062 inventorsTop 30%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #704,053 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
11664427 Vertical semiconductor device with enhanced contact structure and associated methods Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2023-05-30
11387325 Vertical semiconductor device with enhanced contact structure and associated methods Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2022-07-12
10879356 Method for making a semiconductor device including enhanced contact structures having a superlattice Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2020-12-29
10777451 Semiconductor device including enhanced contact structures having a superlattice Robert John Stephenson, Richard Burton, Dmitri A. Choutov, Nyles Wynn Cody, Daniel J. Connelly +1 more 2020-09-15
9972685 Vertical semiconductor devices including superlattice punch through stop layer and related methods Robert J. Mears, Hideki Takeuchi 2018-05-15
9406753 Semiconductor devices including superlattice depletion layer stack and related methods Robert J. Mears, Hideki Takeuchi 2016-08-02
9275996 Vertical semiconductor devices including superlattice punch through stop layer and related methods Robert J. Mears, Hideki Takeuchi 2016-03-01