Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10741436 | Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface | Robert John Stephenson, Scott A. Kreps, Robert J. Mears | 2020-08-11 |
| 10636879 | Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice | — | 2020-04-28 |
| 10367064 | Semiconductor device with recessed channel array transistor (RCAT) including a superlattice | — | 2019-07-30 |
| 7928425 | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods | — | 2011-04-19 |
| 7812339 | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures | Robert J. Mears | 2010-10-12 |
| 7781827 | Semiconductor device with a vertical MOSFET including a superlattice and related methods | — | 2010-08-24 |
| 7659539 | Semiconductor device including a floating gate memory cell with a superlattice channel | Scott A. Kreps | 2010-02-09 |
| 7586116 | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice | Scott A. Kreps | 2009-09-08 |
| 7514328 | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween | — | 2009-04-07 |
| 7491587 | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer | — | 2009-02-17 |
| 7446002 | Method for making a semiconductor device comprising a superlattice dielectric interface layer | Robert J. Mears, Marek Hytha, Scott A. Kreps, Robert John Stephenson, Jean Augustin Chan Sow Fook Yiptong +3 more | 2008-11-04 |
| 7202494 | FINFET including a superlattice | Richard A. Blanchard, Scott A. Kreps | 2007-04-10 |
| 6297130 | Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS isolation methods | — | 2001-10-02 |
| 6239003 | Method of simultaneous fabrication of isolation and gate regions in a semiconductor device | Richard L. Guldi, Kueing-Long Chen | 2001-05-29 |
| 5608256 | Recessed sidewall-sealed and sandwiched poly-buffered LOCOS isolation regions, VLSI structures and methods | — | 1997-03-04 |
| 5369051 | Sidewall-sealed poly-buffered LOCOS isolation | Joel T. Tomlin, Monica A. Beals | 1994-11-29 |
| 5298451 | Recessed and sidewall-sealed poly-buffered LOCOS isolation methods | — | 1994-03-29 |
| 5294563 | Sidewall-sealed and sandwiched poly-buffered locos isolation methods | — | 1994-03-15 |
| 5159428 | Sidewall-sealed poly-buffered LOCOS isolation | Joel T. Tomlin, Monica A. Beals | 1992-10-27 |
| 5114530 | Interlevel dielectric process | Allan T. Mitchell, James L. Paterson | 1992-05-19 |
| 4878996 | Method for reduction of filaments between electrodes | Allan T. Mitchell, Howard L. Tigelaar, Shaym G. Garg | 1989-11-07 |
| 4874716 | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface | — | 1989-10-17 |
| 4806201 | Use of sidewall oxide to reduce filaments | Allan T. Mitchell, Howard L. Tigelaar, Shaym G. Garg | 1989-02-21 |
| 4799992 | Interlevel dielectric fabrication process | Allan T. Mitchell, James L. Paterson | 1989-01-24 |