Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6091149 | Dissolvable dielectric method and structure | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, Mark W. Michael | 2000-07-18 |
| 6067855 | Apparatus and method for measuring liquid level in a sealed container | Ian G. Brown | 2000-05-30 |
| 6060389 | Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect | Frederick N. Hause | 2000-05-09 |
| 6049134 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford | 2000-04-11 |
| 6031289 | Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael | 2000-02-29 |
| 5998293 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1999-12-07 |
| 5968843 | Method of planarizing a semiconductor topography using multiple polish pads | Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1999-10-19 |
| 5953626 | Dissolvable dielectric method | Fred N. Hause, Basab Bandyopadhyay, Robert Dawson, H. Jim Fulford, Mark W. Michael | 1999-09-14 |
| 5926713 | Method for achieving global planarization by forming minimum mesas in large field areas | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael | 1999-07-20 |
| 5926717 | Method of making an integrated circuit with oxidizable trench liner | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1999-07-20 |
| 5924008 | Integrated circuit having local interconnect for reducing signal cross coupled noise | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1999-07-13 |
| 5899727 | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization | Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Mark W. Michael | 1999-05-04 |
| 5894168 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford | 1999-04-13 |
| 5854515 | Integrated circuit having conductors of enhanced cross-sectional area | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael | 1998-12-29 |
| 5854131 | Integrated circuit having horizontally and vertically offset interconnect lines | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford Jr., Fred N. Hause | 1998-12-29 |
| 5851913 | Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process | Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-12-22 |
| 5850105 | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1998-12-15 |
| 5846876 | Integrated circuit which uses a damascene process for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael | 1998-12-08 |
| 5847462 | Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer | Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause, Robert Dawson, Mark W. Michael | 1998-12-08 |
| 5830773 | Method for forming semiconductor field region dielectrics having globally planarized upper surfaces | Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford, Mark W. Michael | 1998-11-03 |
| 5827776 | Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael | 1998-10-27 |
| 5814555 | Interlevel dielectric with air gaps to lessen capacitive coupling | Basab Bandyopadhyay, H. Jim Fulford, Robert Dawson, Fred N. Hause, Mark W. Michael | 1998-09-29 |
| 5792706 | Interlevel dielectric with air gaps to reduce permitivity | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford | 1998-08-11 |
| 5783481 | Semiconductor interlevel dielectric having a polymide for producing air gaps | Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-07-21 |
| 5783864 | Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect | Robert Dawson, Mark W. Michael, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1998-07-21 |