Issued Patents All Time
Showing 51–57 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5767000 | Method of manufacturing subfield conductive layer | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-06-16 |
| 5766803 | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford | 1998-06-16 |
| 5767012 | Method of forming a recessed interconnect structure | H. Jim Fulford, Basab Bandyopadhyay, Robert Dawson, Fred N. Hause, Mark W. Michael | 1998-06-16 |
| 5759913 | Method of formation of an air gap within a semiconductor dielectric by solvent desorption | H. Jim Fulford, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1998-06-02 |
| 5733798 | Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization | Mark W. Michael, Robert Dawson, Fred N. Hause, Basab Bandyopadhyay, H. Jim Fulford | 1998-03-31 |
| 5717242 | Integrated circuit having local interconnect for reduing signal cross coupled noise | Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Fred N. Hause | 1998-02-10 |
| 5679605 | Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process | Robert Dawson, H. Jim Fulford, Fred N. Hause, Basab Bandyopadhyay, Mark W. Michael | 1997-10-21 |