Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Venu M. Kondapalli

AMAMD: 34 patents #265 of 9,279Top 3%
INIntel: 1 patents #18,218 of 30,777Top 60%
San Jose, CA: #1,653 of 32,062 inventorsTop 6%
California: #13,801 of 386,348 inventorsTop 4%
Overall (All Time): #96,086 of 4,157,543Top 3%
35 Patents All Time

Issued Patents All Time

Showing 26–35 of 35 patents

Patent #TitleCo-InventorsDate
6753722 Method and apparatus for voltage regulation within an integrated circuit Martin L. Voogel, Philip D. Costello 2004-06-22
6448809 FPGA with a plurality of input reference voltage levels F. Erich Goetting, Scott O. Frake, Steven P. Young 2002-09-10
6441641 Programmable logic device with partial battery backup Raymond C. Pang, Jane W. Sowards, Scott O. Frake, Jennifer Wong, F. Erich Goetting +2 more 2002-08-27
6366117 Nonvolatile/battery-backed key in PLD Raymond C. Pang, Jennifer Wong, Scott O. Frake, Jane W. Sowards, F. Erich Goetting +2 more 2002-04-02
6294930 FPGA with a plurality of input reference voltage levels F. Erich Goetting, Scott O. Frake, Steven P. Young 2001-09-25
6204691 FPGA with a plurality of input reference voltage levels grouped into sets F. Erich Goetting, Scott O. Frake, Steven P. Young 2001-03-20
6049227 FPGA with a plurality of I/O voltage levels F. Erich Goetting, Scott O. Frake, Steven P. Young 2000-04-11
5958026 Input/output buffer supporting multiple I/O standards F. Erich Goetting, Scott O. Frake 1999-09-28
5877632 FPGA with a plurality of I/O voltage levels F. Erich Goetting, Scott O. Frake, Steven P. Young 1999-03-02
5694047 Method and system for measuring antifuse resistance F. Erich Goetting, David P. Schultz 1997-12-02