Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6998301 | Method for forming a tri-gate MOSFET | Bin Yu | 2006-02-14 |
| 6995438 | Semiconductor device with fully silicided source/drain and damascence metal gate | Haihong Wang, Bin Yu | 2006-02-07 |
| 6982464 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Haihong Wang, Bin Yu | 2006-01-03 |
| 6974983 | Isolated FinFET P-channel/N-channel transistor pair | Wiley Eugene Hill, Haihong Wang, Bin Yu | 2005-12-13 |
| 6967175 | Damascene gate semiconductor processing with local thinning of channel region | Haihong Wang, Bin Yu | 2005-11-22 |
| 6960804 | Semiconductor device having a gate structure surrounding a fin | Chih-Yuh Yang, Judy Xilin An, Srikanteswara Dakshina-Murthy, Bin Yu | 2005-11-01 |
| 6958512 | Non-volatile memory device | Yider Wu, Haihong Wang, Bin Yu | 2005-10-25 |
| 6936882 | Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages | Haihong Wang, Bin Yu | 2005-08-30 |
| 6914277 | Merged FinFET P-channel/N-channel pair | Wiley Eugene Hill, Haihong Wang, Bin Yu | 2005-07-05 |
| 6894337 | System and method for forming stacked fin structure using metal-induced-crystallization | Haihong Wang, Bin Yu | 2005-05-17 |
| 6876042 | Additional gate control for a double-gate MOSFET | Bin Yu, Haihong Wang | 2005-04-05 |
| 6855607 | Multi-step chemical mechanical polishing of a gate area in a FinFET | Krishnashree Achuthan, Haihong Wang, Bin Yu | 2005-02-15 |
| 6855989 | Damascene finfet gate with selective metal interdiffusion | Haihong Wang, Ming-Ren Lin, Bin Yu | 2005-02-15 |
| 6833588 | Semiconductor device having a U-shaped gate structure | Bin Yu, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang | 2004-12-21 |
| 6812076 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Haihong Wang, Bin Yu | 2004-11-02 |
| 6812119 | Narrow fins by oxidation in double-gate finfet | Ming-Ren Lin, Haihong Wang, Bin Yu | 2004-11-02 |
| 6787406 | Systems and methods for forming dense n-channel and p-channel fins using shadow implanting | Wiley Eugene Hill, Haihong Wang, Bin Yu | 2004-09-07 |
| 6787439 | Method using planarizing gate material to improve gate critical dimension in semiconductor devices | Cyrus E. Tabery, Haihong Wang, Bin Yu | 2004-09-07 |
| 6787854 | Method for forming a fin in a finFET device | Chih-Yuh Yang, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu | 2004-09-07 |
| 6756643 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Haihong Wang, Bin Yu | 2004-06-29 |
| 6686231 | Damascene gate process with sacrificial oxide in semiconductor devices | Haihong Wang, Bin Yu | 2004-02-03 |
| 6611029 | Double gate semiconductor device having separate gates | Haihong Wang, Bin Yu | 2003-08-26 |