Issued Patents All Time
Showing 51–75 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6381163 | Methods and apparatus for reading a CAM cell using boosted and regulated gate voltage | Kazuhiro Kurihara | 2002-04-30 |
| 6373742 | Two side decoding of a memory array | Kazuhiro Kurihara, Pau-Ling Chen | 2002-04-16 |
| 6275414 | Uniform bitline strapping of a non-volatile memory cell | Mark Randolph, Pau-Ling Chen, Richard Fastow | 2001-08-14 |
| 6272043 | Apparatus and method of direct current sensing from source side in a virtual ground array | — | 2001-08-07 |
| 6269025 | Memory system having a program and erase voltage modifier | Binh Quang Le, Pau-Ling Chen | 2001-07-31 |
| 6266275 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory | Paul L. Chen, Mike Van Buskirk, Binh Quang Le, Shoichi Kawamura, Chung-You Hu +3 more | 2001-07-24 |
| 6262469 | Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor | Binh Quang Le, Pau-Ling Chen | 2001-07-17 |
| 6240020 | Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices | Andrew Yang, Pau-Ling Chen | 2001-05-29 |
| 6222768 | Auto adjusting window placement scheme for an NROM virtual ground array | Pau-Ling Chen | 2001-04-24 |
| 6215702 | Method of maintaining constant erasing speeds for non-volatile memory cells | Narbeh Derhacobian, Ravi Sunkavalli | 2001-04-10 |
| 6201737 | Apparatus and method to characterize the threshold distribution in an NROM virtual ground array | Kazuhiro Kurihara | 2001-03-13 |
| 6185130 | Programmable current source | Joseph G. Pawletko | 2001-02-06 |
| 6181605 | Global erase/program verification apparatus and method | Joseph G. Pawletko, Michael Chung | 2001-01-30 |
| 6175523 | Precharging mechanism and method for NAND-based flash memory devices | Andrew Yang, Binh Quang Le | 2001-01-16 |
| 6141244 | Multi level sensing of NAND memory cells by external bias current | Joseph G. Pawletko, Pau-Ling Chen | 2000-10-31 |
| 6137153 | Floating gate capacitor for use in voltage regulators | Binh Quang Le, Pau-Ling Chen | 2000-10-24 |
| 6117179 | High voltage electrical rule check program | Alexius H. Tan, Jonathan Su | 2000-09-12 |
| 6081455 | EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block | Binh Quang Le, Pau-Ling Chen | 2000-06-27 |
| 6072725 | Method of erasing floating gate capacitor used in voltage regulator | Binh Quang Le, Pau-Ling Chen | 2000-06-06 |
| 6055366 | Methods and apparatus to perform high voltage electrical rule check of MOS circuit design | Binh Quang Le, Pau-Ling Chen, Alexius H. Tan | 2000-04-25 |
| 6009014 | Erase verify scheme for NAND flash | Chung-You Hu, Binh Quang Le, Pau-Ling Chen, Jonathan S. Su, Ravi Prakash Gutala +1 more | 1999-12-28 |
| 6005804 | Split voltage for NAND flash | Binh Quang Le, Pau-Ling Chen | 1999-12-21 |
| 5999452 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory | Pau-Ling Chen, Mike Van Buskirk, Binh Quang Le, Shoichi Kawamura, Chung-You Hu +3 more | 1999-12-07 |
| 5995417 | Scheme for page erase and erase verify in a non-volatile memory array | Pau-Ling Chen, Michael Chung, Vincent Leung, Binh Quang Le, Masaru Yano | 1999-11-30 |
| 5978267 | Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same | Pau-Ling Chen, Michael A. Van Buskirk, Michael Chung, Binh Quang Le, Vincent Leung +2 more | 1999-11-02 |