Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5789295 | Method of eliminating or reducing poly1 oxidation at stacked gate edge in flash EPROM process | — | 1998-08-04 |
| 5693972 | Method and system for protecting a stacked gate edge in a semiconductor device from self-aligned source (sas) etch in a semiconductor device | — | 1997-12-02 |
| 5674764 | Method of making asymmetric non-volatile memory cell | Man Wong | 1997-10-07 |
| 5656509 | Method and test structure for determining gouging in a flash EPROM cell during SAS etch | — | 1997-08-12 |
| 5652155 | Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant | Ming Sang Kwan, Chi Chang | 1997-07-29 |
| 5650964 | Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge | Jian Chen, James Hsu, Shengwen Luan, Yuan Tang, Michael A. Van Buskirk | 1997-07-22 |
| 5646430 | Non-volatile memory cell having lightly-doped source region | Cetin Kaya | 1997-07-08 |
| 5625220 | Sublithographic antifuse | Kueing-Long Chen, Bert R. Riemenschneider | 1997-04-29 |
| 5624859 | Method for providing device isolation and off-state leakage current for a semiconductor device | Mark T. Ramsbey | 1997-04-29 |
| 5612914 | Asymmetrical non-volatile memory cell, arrays and methods for fabricating same | Man Wong | 1997-03-18 |
| 5596531 | Method for decreasing the discharge time of a flash EPROM cell | Ming Sang Kwan, Chi Chang, Sameer Haddad, Yuan Tang | 1997-01-21 |
| 5590076 | Channel hot-carrier page write | Sameer Haddad, Chi Chang | 1996-12-31 |
| 5541875 | High energy buried layer implant to provide a low resistance p-well in a flash EPROM array | Jian Chen | 1996-07-30 |
| 5534455 | Method for protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch | — | 1996-07-09 |
| 5521867 | Adjustable threshold voltage conversion circuit | Jian Chen, Lee Cleveland, Shane Hollmer, Ming Sang Kwan, Nader Radjy | 1996-05-28 |
| 5517443 | Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device | Yu Sun, Chi Chang | 1996-05-14 |
| 5482880 | Non-volatile memory cell and fabrication method | Cetin Kaya | 1996-01-09 |
| 5470773 | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch | Yu Sun, Chi Chang | 1995-11-28 |
| 5395797 | Antifuse structure and method of fabrication | Kueing-Long Chen, Ashwin H. Shah | 1995-03-07 |
| 5371402 | Low capacitance, low resistance sidewall antifuse structure and process | Man Wong | 1994-12-06 |
| 5365105 | Sidewall anti-fuse structure and method for making | Kueing-Long Chen, Bert R. Riemenschneider | 1994-11-15 |
| 5300803 | Source side injection non-volatile memory cell | — | 1994-04-05 |
| 5264384 | Method of making a non-volatile memory cell | Cetin Kaya | 1993-11-23 |
| 5250464 | Method of making a low capacitance, low resistance sidewall antifuse structure | Man Wong | 1993-10-05 |
| 5219782 | Sublithographic antifuse method for manufacturing | Kueing-Long Chen | 1993-06-15 |