Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6011272 | Silicided shallow junction formation and structure with high and low breakdown voltages | Farrokh Omid-Zohoor | 2000-01-04 |
| 5978272 | Nonvolatile memory structure for programmable logic devices | Hao Fang, Sameer Haddad | 1999-11-02 |
| 5973372 | Silicided shallow junction transistor formation and structure with high and low breakdown voltages | Farrokh Omid-Zohoor | 1999-10-26 |
| 5966329 | Apparatus and method for programming PMOS memory cells | Ching-Hsiang Hsu, Shang-De Ted Chang | 1999-10-12 |
| 5912842 | Nonvolatile PMOS two transistor memory cell and array | Shang-De Ted Chang, Vikram Kowshik, Andy Yu | 1999-06-15 |
| 5598369 | Flash EEPROM array with floating substrate erase operation | Jian Chen | 1997-01-28 |
| 5579261 | Reduced column leakage during programming for a flash memory array | Lee Cleveland, Jian Chen, Shane Hollmer | 1996-11-26 |
| 5576991 | Multistepped threshold convergence for a flash memory array | Lee Cleveland, Jian Chen, Shane Hollmer | 1996-11-19 |
| 5561620 | Flash EEPROM array with floating substrate erase operation | Jian Chen | 1996-10-01 |
| 5521867 | Adjustable threshold voltage conversion circuit | Jian Chen, Lee Cleveland, Shane Hollmer, Ming Sang Kwan, David Kuan-Yu Liu | 1996-05-28 |
| 5231602 | Apparatus and method for improving the endurance of floating gate devices | Michael S. Briner | 1993-07-27 |
| 5191556 | Method of page-mode programming flash EEPROM cell arrays | — | 1993-03-02 |
| 5101378 | Optimized electrically erasable cell for minimum read disturb and associated method of sensing | Michael S. Briner | 1992-03-31 |
| 5005155 | Optimized electrically erasable PLA cell for minimum read disturb | Michael S. Briner | 1991-04-02 |
| 4935648 | Optimized E.sup.2 pal cell for minimum read disturb | Michael S. Briner | 1990-06-19 |