Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7072781 | Architecture for generating adaptive arbitrary waveforms | Eugen Gershon, David Gaun, Tzu-Ning Fang | 2006-07-04 |
| 7035141 | Diode array architecture for addressing nanoscale resistive memory arrays | Nicholas H. Tripsas, Michael VanBuskirk, Matthew S. Buynoski, Tzu-Ning Fang, Wei Daisy Cai +2 more | 2006-04-25 |
| 7028240 | Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine | Edward V. Bautista, Jr., Ken Cheong Cheah | 2006-04-11 |
| 7010736 | Address sequencer within BIST (Built-in-Self-Test) system | Boon Tang Teh, Edward V. Bautista, Jr., Ken Cheong Cheah, Joseph Kucera, Weng Fook Lee +1 more | 2006-03-07 |
| 6960783 | Erasing and programming an organic memory device and method of fabricating | Zhida Lan, Michael VanBuskirk | 2005-11-01 |
| 6943370 | Control of memory arrays utilizing zener diode-like devices | Michael VanBuskirk, Tzu-Ning Fang, Zhida Lan | 2005-09-13 |
| 6847047 | Methods that facilitate control of memory arrays utilizing zener diode-like devices | Michael VanBuskirk, Tzu-Ning Fang, Zhida Lan | 2005-01-25 |
| 6707718 | Generation of margining voltage on-chip during testing CAM portion of flash memory device | Azrul Halim, Ken Cheong Cheah, Syahrizal Salleh | 2004-03-16 |
| 6631086 | On-chip repair of defective address of core flash memory cells | Ken Cheong Cheah, Edward V. Bautista, Jr., Azrul Halim, Darlene Hamilton | 2003-10-07 |
| 6622274 | Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization | Weng Fook Lee, Feng Pan, Edward V. Bautista, Jr. | 2003-09-16 |
| 6587982 | Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling | Weng Fook Lee, Feng Pan, Edward V. Bautista, Jr., Azrul Halim | 2003-07-01 |
| 6459625 | Three metal process for optimizing layout density | Jonathan Su, Ravi Prakash Gutala | 2002-10-01 |
| 6449190 | Adaptive reference cells for a memory device | — | 2002-09-10 |
| 6438041 | Negative voltage regulation | Shigekazu Yamada | 2002-08-20 |
| 6430087 | Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage | Ravi Prakash Gutala | 2002-08-06 |
| 6400638 | Wordline driver for flash memory read mode | Shigekazu Yamada, Takao Akaogi | 2002-06-04 |
| 6370065 | Serial sequencing of automatic program disturb erase verify during a fast erase mode | Feng Pan | 2002-04-09 |
| 6359824 | Activation of wordline decoders to transfer a high voltage supply | Jonathan Su, Feng Pan | 2002-03-19 |
| 6324108 | Application of external voltage during array VT testing | Edward V. Bautista, Jr., Shigekazu Yamada | 2001-11-27 |
| 6285594 | Wordline voltage protection | Edward V. Bautista, Jr., Santosh Yachareni | 2001-09-04 |
| 6275415 | Multiple byte channel hot electron programming using ramped gate and source bias voltage | Sameer Haddad, Ravi Sunkavalli, Wing Leung, John Chen, Ravi Prakash Gutala +1 more | 2001-08-14 |
| 6205059 | Method for erasing flash electrically erasable programmable read-only memory (EEPROM) | Ravi Prakash Gutala, Jonathan S. Su | 2001-03-20 |
| 6205056 | Automated reference cell trimming verify | Feng Pan | 2001-03-20 |
| 6172914 | Concurrent erase verify scheme for flash memory applications | Sameer Haddad, Michael A. Van Buskirk | 2001-01-09 |
| 6163481 | Flash memory wordline tracking across whole chip | Shigekasu Yamada, Michael VanBuskirk | 2000-12-19 |