Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8185720 | Processor block ASIC core for embedding in an integrated circuit | Jeffery H. Appelbaum, Kam-Wing Li, James J. Murray, Kathryn Story Purcell, Alex S. Warshofsky | 2012-05-22 |
| 8019950 | Memory controller interface for an embedded processor block core in an integrated circuit | Alex S. Warshofsky | 2011-09-13 |
| 8006021 | Processor local bus bridge for an embedded processor block core in an integrated circuit | Kam-Wing Li, Jeffery H. Appelbaum | 2011-08-23 |
| 7970977 | Deadlock-resistant bus bridge with pipeline-restricted address ranges | Kam-Wing Li, Sanford L. Helton, Tomai Knopp, Khang K. Dao, Jeffrey H. Seltzer | 2011-06-28 |
| 7958414 | Enhancing security of internal memory | Ting Lu, Ismed D. Hartanto | 2011-06-07 |
| 7865698 | Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions | Kathryn Story Purcell | 2011-01-04 |
| 7788470 | Shadow pipeline in an auxiliary processor unit controller | Kathryn Story Purcell, Gaurav Gupta | 2010-08-31 |
| 7737725 | Device control register for a processor block | Kam-Wing Li | 2010-06-15 |
| 7730244 | Translation of commands in an interconnection of an embedded processor block core in an integrated circuit | Jeffery H. Appelbaum, Kam-Wing Li, James J. Murray | 2010-06-01 |
| 7724028 | Clocking for a hardwired core embedded in a host integrated circuit device | Alex S. Warshofsky | 2010-05-25 |
| 7673087 | Arbitration for an embedded processor block core in an integrated circuit | Jeffery H. Applebaum, Kunal Ramachandra Shenoy | 2010-03-02 |
| 7624209 | Method of and circuit for enabling variable latency data transfers | Mehul R. Vashi, Alex S. Warshofsky | 2009-11-24 |
| 7610469 | Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer | — | 2009-10-27 |
| 7590822 | Tracking an instruction through a processor pipeline | Kathryn Story Purcell | 2009-09-15 |
| 7590823 | Method and system for handling an instruction not supported in a coprocessor formed using configurable logic | Kathryn Story Purcell | 2009-09-15 |
| 7546441 | Coprocessor interface controller | Kathryn Story Purcell | 2009-06-09 |
| 7539848 | Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor | Stephen M. Douglass | 2009-05-26 |
| 7406670 | Testing of an integrated circuit having an embedded processor | Mehul R. Vashi, Nigel G. Herron, Stephen M. Douglass | 2008-07-29 |
| 7346759 | Decoder interface | Kathryn Story Purcell | 2008-03-18 |
| 7313794 | Method and apparatus for synchronization of shared memory in a multiprocessor system | — | 2007-12-25 |
| 7269805 | Testing of an integrated circuit having an embedded processor | Mehul R. Vashi, Nigel G. Herron, Stephen M. Douglass | 2007-09-11 |
| 7243212 | Processor-controller interface for non-lock step operation | Kathryn Story Purcell | 2007-07-10 |
| 7231621 | Speed verification of an embedded processor in a programmable logic device | Nigel G. Herron, Stephen M. Douglass, Anthony Correale, Jr., Leslie Mark DeBruyne | 2007-06-12 |
| 7200723 | Access to a bank of registers of a device control register interface using a single address | Kathryn Story Purcell | 2007-04-03 |
| 7194600 | Method and apparatus for processing data with a programmable gate array using fixed and programmable processors | Stephen M. Douglass | 2007-03-20 |