Issued Patents 2025
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424576 | Integrated circuit package and method | Chen-Hua Yu, Shih-Ting Lin, Szu-Wei Lu | 2025-09-23 |
| 12418001 | 3D integrated circuit (3DIC) structure | Chen-Hua Yu, Chung-Shi Liu | 2025-09-16 |
| 12374651 | Wafer bonding method | Yung-Chi Lin, Tsang-Jiuh Wu, Chen-Hua Yu | 2025-07-29 |
| 12374655 | Method of forming package structure by using a wafer chuck with adjustable curved surface | Yung-Chi Lin, Yen-Ming Chen | 2025-07-29 |
| 12366004 | Apparatus and method for wafer pre-wetting | Chen-Yu Tsai, Ku-Feng Yang | 2025-07-22 |
| 12362315 | Heterogeneous dielectric bonding scheme | Chen-Hua Yu, Ku-Feng Yang, Ming-Tsu Chung | 2025-07-15 |
| 12347739 | Package structure | Chih-Wei Wu, Ying-Ching Shih | 2025-07-01 |
| 12322680 | Semiconductor device having backside interconnect structure on through substrate via | Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih +3 more | 2025-06-03 |
| 12276838 | Semiconductor device and manufacturing method thereof having grating coupled dies and nanostructures | Yu-Kuang Liao, Jia-Xsing Li, Ping-Jung Wu, Tsang-Jiuh Wu, Chen-Hua Yu | 2025-04-15 |
| 12278203 | Semiconductor structure and manufacturing method thereof | Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu | 2025-04-15 |
| 12261151 | Integrated circuit packages | Chia-Hao Hsu, Yung-Chi Lin | 2025-03-25 |
| 12237284 | Semiconductor structure comprising dummy feature interposed between the bonding connectors | Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu | 2025-02-25 |
| 12227867 | Plating apparatus for plating semiconductor wafer and plating method | Chen-Yu Tsai, Ku-Feng Yang | 2025-02-18 |
| 12218022 | Passivation structure with planar top surfaces | Yi-Hsiu Chen, Chen-Hua Yu | 2025-02-04 |