Issued Patents 2025
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369399 | Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure | Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic +2 more | 2025-07-22 |
| 12342614 | Asymmetric gate structures and contacts for stacked transistors | Cheng-Ying Huang, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady, Nicole K. Thomas +2 more | 2025-06-24 |
| 12310044 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2025-05-20 |
| 12288810 | Backside contact structures and fabrication for metal on both sides of devices | Rishabh Mehandru, Aaron D. Lilak, Kimin Jun | 2025-04-29 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Anh Phan, Willy Rachmady +3 more | 2025-03-18 |
| 12224202 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more | 2025-02-11 |
| 12199143 | Gate-all-around integrated circuit structures having removed substrate | Biswajeet Guha, Mauro J. Kobrinsky, Oleg Golonzka, Tahir Ghani | 2025-01-14 |