Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12125763 | Trim wall protection method for multi-wafer stacking | Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai | 2024-10-22 |
| 12087756 | Protective wafer grooving structure for wafer thinning and methods of using the same | Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai | 2024-09-10 |
| 12062687 | Semiconductor device including a capacitor | Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen +1 more | 2024-08-13 |
| 11984431 | 3DIC structure and methods of forming | Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou | 2024-05-14 |
| 11951569 | Damage prevention during wafer edge trimming | Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai | 2024-04-09 |
| 11942543 | Semiconductor device structure with high voltage device | Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin +4 more | 2024-03-26 |
| 11942541 | Semiconductor device and method for forming the same | Hong-Shyang Wu | 2024-03-26 |
| 11935950 | High voltage transistor structure | Po-Yu Chen, Wan-Hua Huang, Jing Chen | 2024-03-19 |
| 11862515 | Multi-wafer capping layer for metal arcing protection | Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li | 2024-01-02 |
| 11862675 | High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device | Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker Hsiao Huo, Po-Chih Chen +5 more | 2024-01-02 |