Issued Patents 2024
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11990477 | Hybrid fin field-effect transistor cell structures and related methods | Wei-An Lai, Hui-Zhong Zhuang, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2024-05-21 |
| 11984443 | Power distribution network | Kam-Tou Sio, Wei-Cheng Lin | 2024-05-14 |
| 11984441 | Integrated circuit with backside power rail and backside interconnect | Shih-Wei Peng, Guo-Huei Wu | 2024-05-14 |
| 11967560 | Integrated circuit | Shih-Wei Peng, Chia-Tien Wu | 2024-04-23 |
| 11948974 | Semiconductor device including vertical transistor with back side power structure | Shih-Wei Peng, Te-Hsin Chiu | 2024-04-02 |
| 11942469 | Backside conducting lines in integrated circuits | Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Chung-Hsing Wang | 2024-03-26 |
| 11942470 | Semiconductor device and method for manufacturing the same | Shih-Wei Peng | 2024-03-26 |
| 11942413 | Decoupling capacitors with back side power rails | Kam-Tou Sio | 2024-03-26 |
| 11935830 | Integrated circuit with frontside and backside conductive layers and exposed backside substrate | Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiun-Wei Lu | 2024-03-19 |
| 11935825 | Contact structure, method, layout, and system | Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Wei-Cheng Lin, Lipen Yuan | 2024-03-19 |
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin | 2024-03-05 |
| 11923369 | Integrated circuit, system and method of forming the same | Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai | 2024-03-05 |
| 11923301 | Method of manufacturing semiconductor device | Shih-Wei Peng, Hui-Ting Yang, Wei-Cheng Lin | 2024-03-05 |
| 11923300 | Two-dimensional (2D) metal structure | Shih-Wei Peng, Ken-Hsien Hsieh | 2024-03-05 |
| 11923273 | Method of manufacturing a semiconductor device | Shih-Wei Peng, Chia-Tien Wu | 2024-03-05 |
| 11916074 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin | 2024-02-27 |
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +5 more | 2024-02-27 |
| 11916070 | Semiconductor structure with nanosheets | Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Wei-Cheng Lin | 2024-02-27 |
| 11908538 | Cell structures and power routing for integrated circuits | Shih-Wei Peng, Kam-Tou Sio | 2024-02-20 |
| 11908852 | Layout designs of integrated circuits having backside routing tracks | Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin | 2024-02-20 |
| 11901286 | Diagonal via pattern and method | Shih-Wei Peng, Chih-Min HSIAO, Ching-Hsu Chang | 2024-02-13 |
| 11894375 | Semiconductor structure and method of forming the same | Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin | 2024-02-06 |
| 11893333 | Hybrid sheet layout, method, system, and structure | Shang-Wei Fang, Kam-Tou Sio, Wei-Cheng Lin, Lee-Chung Lu, Yi-Kan Cheng +1 more | 2024-02-06 |
| 11862623 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Shun Li Chen, Kam-Tou Sio +3 more | 2024-01-02 |
| 11862561 | Semiconductor devices with backside routing and method of forming same | Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin +1 more | 2024-01-02 |