Issued Patents 2024
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183788 | Semiconductor arrangement comprising a source pad, gate pad, drain pad, backside interconnect line, and backside contact, and backside conductive line and method of making | Jiann-Tyng Tzeng | 2024-12-31 |
| 12148700 | Semiconductor device, and associated method and system | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-11-19 |
| 12142611 | Semiconductor structure for reducing stray capacitance and method of forming the same | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-11-12 |
| 12142563 | Dual power structure with efficient layout | Jiann-Tyng Tzeng | 2024-11-12 |
| 12131998 | Integrated circuit, system and method of forming same | Te-Hsin Chiu, Kam-Tou Sio, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-10-29 |
| 12101922 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Wei-An Lai | 2024-09-24 |
| 12094777 | Method for manufacturing semiconductor device | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-09-17 |
| 12079559 | IC device layout method | Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Jiann-Tyng Tzeng | 2024-09-03 |
| 12067341 | Semiconductor structure, device, and method | Jiann-Tyng Tzeng, Wei-Cheng Lin | 2024-08-20 |
| 12061856 | Semiconductor device including combination rows and method and system for generating layout diagram of same | Jiann-Tyng Tzeng | 2024-08-13 |
| 12039246 | Circuit layout | Kam-Tou Sio, Jiann-Tyng Tzeng | 2024-07-16 |
| 12021021 | Integrated circuit structure | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-06-25 |
| 12009364 | Semiconductor device and manufacture thereof | Te-Hsin Chiu, Meng-Hung Shen, Jiann-Tyng Tzeng | 2024-06-11 |
| 11984441 | Integrated circuit with backside power rail and backside interconnect | Guo-Huei Wu, Jiann-Tyng Tzeng | 2024-05-14 |
| 11967560 | Integrated circuit | Chia-Tien Wu, Jiann-Tyng Tzeng | 2024-04-23 |
| 11967596 | Power rail and signal conducting line arrangement | Guo-Huei Wu, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien +1 more | 2024-04-23 |
| 11948974 | Semiconductor device including vertical transistor with back side power structure | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2024-04-02 |
| 11942470 | Semiconductor device and method for manufacturing the same | Jiann-Tyng Tzeng | 2024-03-26 |
| 11942469 | Backside conducting lines in integrated circuits | Wei-An Lai, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2024-03-26 |
| 11935830 | Integrated circuit with frontside and backside conductive layers and exposed backside substrate | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu | 2024-03-19 |
| 11923273 | Method of manufacturing a semiconductor device | Chia-Tien Wu, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923301 | Method of manufacturing semiconductor device | Hui-Ting Yang, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923300 | Two-dimensional (2D) metal structure | Jiann-Tyng Tzeng, Ken-Hsien Hsieh | 2024-03-05 |
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Wei-An Lai, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11916074 | Double rule integrated circuit layouts for a dual transmission gate | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin | 2024-02-27 |