Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12101922 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng | 2024-09-24 |
| 12086524 | Semiconductor device having more similar cell densities in alternating rows | Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan | 2024-09-10 |
| 12068305 | Multiple fin height integrated circuit | Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan | 2024-08-20 |
| 11990477 | Hybrid fin field-effect transistor cell structures and related methods | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2024-05-21 |
| 11942469 | Backside conducting lines in integrated circuits | Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2024-03-26 |
| 11923369 | Integrated circuit, system and method of forming the same | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +5 more | 2024-02-27 |
| 11908852 | Layout designs of integrated circuits having backside routing tracks | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-02-20 |