Issued Patents 2024
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170273 | Integrated circuit assemblies with direct chip attach to circuit boards | Wilfred Gomes, Sanka Ganesan, Abhishek A. Sharma, Doug B. Ingerly, Kevin J. Fischer | 2024-12-17 |
| 12148751 | Use of a placeholder for backside contact formation for transistor arrangements | Andy Wei, Anand S. Murthy, Guillaume Bouche | 2024-11-19 |
| 12147083 | Hybrid manufacturing for integrating photonic and electronic components | Abhishek A. Sharma, Wilfred Gomes | 2024-11-19 |
| 12114479 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot N. Tan +2 more | 2024-10-08 |
| 12107170 | Transistor channel passivation with 2D crystalline material | Carl Naylor, Abhishek A. Sharma, Christopher J. Jezewski, Urusa Alaan, Justin R. Weber | 2024-10-01 |
| 12100705 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Rishabh Mehandru, Tahir Ghani, Mark Bohr, Marni Nabors | 2024-09-24 |
| 12058849 | Three-dimensional nanoribbon-based dynamic random-access memory | Wilfred Gomes, Kinyip Phoa, Tahir Ghani, Uygar E. Avci, Rajesh Kumar | 2024-08-06 |
| 11996362 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mark Bohr, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar | 2024-05-28 |
| 11985909 | Fabrication of stackable embedded eDRAM using a binary alloy based on antimony | Elijah V. Karpov | 2024-05-14 |
| 11948874 | Vertically spaced intra-level interconnect line metallization for integrated circuit devices | Kevin Lin, Sukru YEMENICIOGLU, Patrick Morrow, Richard E. Schenker | 2024-04-02 |
| 11901347 | Microelectronic package with three-dimensional (3D) monolithic memory die | Wilfred Gomes, Doug B. Ingerly, Tahir Ghani | 2024-02-13 |
| 11881452 | Device layer interconnects | Mark Bohr, Marni Nabors | 2024-01-23 |