Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159901 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Anand S. Murthy, Mark Bohr, Tahir Ghani, Biswajeet Guha | 2024-12-03 |
| 12027585 | Source or drain structures with low resistivity | Anand S. Murthy, Suresh Vishwanath | 2024-07-02 |
| 12027417 | Source or drain structures with high germanium concentration capping layer | Suresh Vishwanath, Yulia Tolstova, Pratik A. Patel, Szuya S. Liao, Anand S. Murthy | 2024-07-02 |
| 12021149 | Fin smoothing and integrated circuit structures resulting therefrom | Anand S. Murthy, Tahir Ghani, Anupama Bowonder | 2024-06-25 |
| 11996404 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more | 2024-05-28 |
| 11990513 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Anand S. Murthy, Susmita Ghose, Siddharth Chouksey | 2024-05-21 |
| 11984449 | Channel structures with sub-fin dopant diffusion blocking layers | Anand S. Murthy, Stephen M. Cea, Biswajeet Guha, Anupama Bowonder, Tahir Ghani | 2024-05-14 |
| 11978784 | Gate-all-around integrated circuit structures having germanium nanowire channel structures | Anand S. Murthy, Susmita Ghose, Zachary Geiger | 2024-05-07 |
| 11929320 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Gilbert Dewey, Ryan Keech, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady +1 more | 2024-03-12 |
| 11887988 | Thin film transistor structures with regrown source and drain | Ashish Agrawal, Jack T. Kavalieros, Anand S. Murthy, Gilbert Dewey, Matthew V. Metz +2 more | 2024-01-30 |